公开(公告)号：US10014208B2

公开(公告)日：2018-07-03

申请号：US15444567

申请日：2017-02-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Youn Kim ,  Min-Choul Kim ,  Baik-Min Sung ,  Sang-Hyun Woo

IPC: H01L27/088 ,  H01L21/762 ,  H01L27/092

CPC classification number: H01L21/76224 ,  H01L21/76232 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device includes a fin protruding from a substrate and extending in a first direction, first and second gate structures intersecting the fin, a recess formed in the fin between the first and second gate structures, a device isolation layer which fills the recess, and which has an upper surface protruded outwardly from the fin and disposed to be coplanar with upper surfaces of the first and second gate structures, a liner formed along a side walls of the device isolation layer protruded outwardly from the fin and a source/drain region disposed at both sides of the recess and spaced apart from the device isolation layer.

公开(公告)号：US20160380052A1

公开(公告)日：2016-12-29

申请号：US15015937

申请日：2016-02-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JU-YOUN KIM ,  Min-Choul Kim ,  Baik-Min Sung ,  Sang-Hyun Woo

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L21/76224 ,  H01L21/76232 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device includes a fin protruding from a substrate and extending in a first direction, first and second gate structures intersecting the fin, a recess formed in the fin between the first and second gate structures, a device isolation layer which fills the recess, and which has an upper surface protruded outwardly from the fin and disposed to be coplanar with upper surfaces of the first and second gate structures, a liner formed along a side walls of the device isolation layer protruded outwardly from the fin and a source/drain region disposed at both sides of the recess and spaced apart from the device isolation layer.

Abstract translation: 半导体器件包括从基板突出并沿第一方向延伸的翅片，与翅片相交的第一和第二栅极结构，形成在第一和第二栅极结构之间的翅片中的凹部，填充凹部的器件隔离层和 其具有从所述翅片向外突出并且设置成与所述第一和第二栅极结构的上表面共面的上表面，沿着从所述鳍片向外突出的所述器件隔离层的侧壁形成的衬垫和设置在所述第二栅极结构的源极/漏极区域 在凹槽的两侧并与器件隔离层隔开。

公开(公告)号：US09614035B2

公开(公告)日：2017-04-04

申请号：US15015937

申请日：2016-02-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Youn Kim ,  Min-Choul Kim ,  Baik-Min Sung ,  Sang-Hyun Woo

IPC: H01L21/70 ,  H01L29/06 ,  H01L29/78 ,  H01L27/092

CPC classification number: H01L21/76224 ,  H01L21/76232 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device includes a fin protruding from a substrate and extending in a first direction, first and second gate structures intersecting the fin, a recess formed in the fin between the first and second gate structures, a device isolation layer which fills the recess, and which has an upper surface protruded outwardly from the fin and disposed to be coplanar with upper surfaces of the first and second gate structures, a liner formed along a side walls of the device isolation layer protruded outwardly from the fin and a source/drain region disposed at both sides of the recess and spaced apart from the device isolation layer.

公开(公告)号：US09496192B2

公开(公告)日：2016-11-15

申请号：US14326471

申请日：2014-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-Lim Kang ,  Min-Ho Kwon ,  Wei-Hua Hsu ,  Sang-Hyun Woo ,  Hwa-Sung Rhee ,  Jun-Suk Choi

IPC: H01L27/088 ,  H01L21/66

CPC classification number: H01L22/34 ,  H01L27/0886

Abstract: A test pattern of a semiconductor device is provided, which includes first and second fins formed to project from a substrate and arranged to be spaced apart from each other, first and second gate structures formed to cross the first and second fins, respectively, a first source region and a first drain region arranged on the first fin on one side and the other side of the first gate structure, a second source region and a second drain region arranged on the second fin on one side and the other side of the second gate structure, a first conductive pattern connected to the first and second drain regions to apply a first voltage to the first and second drain regions and a second conductive pattern connecting the first source region and the second gate structure to each other.

Abstract translation: 提供了一种半导体器件的测试图案，其包括形成为从衬底突出并布置成彼此间隔开的第一和第二鳍片，分别形成为跨越第一和第二鳍片的第一和第二栅极结构，第一和第二鳍片 源极区域和布置在第一鳍片的第一栅极结构的一侧和另一侧上的第一漏极区域，在第二栅极的一侧和另一侧上布置在第二鳍片上的第二源极区域和第二漏极区域 结构，连接到第一和第二漏极区域以将第一电压施加到第一和第二漏极区域的第一导电图案以及将第一源极区域和第二栅极结构彼此连接的第二导电图案。