Semiconductor device
    1.
    发明授权

    公开(公告)号:US11183496B2

    公开(公告)日:2021-11-23

    申请号:US16366140

    申请日:2019-03-27

    Abstract: Semiconductor devices are provided. The semiconductor device includes an active fin which extends along a first direction and has a protruding shape, a gate structure which is disposed on the active fin to extend along a second direction intersecting the first direction, and a spacer which is disposed on at least one side of the gate structure, wherein the gate structure includes a first area and a second area which is adjacent to the first area in the second direction, wherein a first width of the first area in the first direction is different from a second width of the second area in the first direction, and the spacer extends continuously along both the first area and the second area.

    Semiconductor devices and methods of manufacturing the same

    公开(公告)号:US09984886B2

    公开(公告)日:2018-05-29

    申请号:US15001568

    申请日:2016-01-20

    Abstract: A semiconductor device includes a gate structure extending in a second direction on a substrate, a source/drain layer disposed on a portion of the substrate adjacent the gate structure in a first direction crossing the second direction, a first conductive contact plug on the gate structure, and a second contact plug structure disposed on the source/drain layer. The second contact plug structure includes a second conductive contact plug and an insulation pattern, and the second conductive contact plug and the insulation pattern are disposed in the second direction and contact each other. The first conductive contact plug and the insulation pattern are adjacent to each other in the first direction. The first and second conductive contact plugs are spaced apart from each other.

    Semiconductor devices and methods of manufacturing the same

    公开(公告)号:US10410871B2

    公开(公告)日:2019-09-10

    申请号:US15969137

    申请日:2018-05-02

    Abstract: A semiconductor device includes a gate structure extending in a second direction on a substrate, a source/drain layer disposed on a portion of the substrate adjacent the gate structure in a first direction crossing the second direction, a first conductive contact plug on the gate structure, and a second contact plug structure disposed on the source/drain layer. The second contact plug structure includes a second conductive contact plug and an insulation pattern, and the second conductive contact plug and the insulation pattern are disposed in the second direction and contact each other. The first conductive contact plug and the insulation pattern are adjacent to each other in the first direction. The first and second conductive contact plugs are spaced apart from each other.

    Semiconductor device
    5.
    发明授权

    公开(公告)号:US10276567B2

    公开(公告)日:2019-04-30

    申请号:US15014291

    申请日:2016-02-03

    Abstract: Semiconductor devices are provided. The semiconductor device includes an active fin which extends along a first direction and has a protruding shape, a gate structure which is disposed on the active fin to extend along a second direction intersecting the first direction, and a spacer which is disposed on at least one side of the gate structure, wherein the gate structure includes a first area and a second area which is adjacent to the first area in the second direction, wherein a first width of the first area in the first direction is different from a second width of the second area in the first direction, and the spacer extends continuously along both the first area and the second area.

    Test pattern of semiconductor device
    6.
    发明授权
    Test pattern of semiconductor device 有权
    半导体器件的测试图案

    公开(公告)号:US09496192B2

    公开(公告)日:2016-11-15

    申请号:US14326471

    申请日:2014-07-09

    CPC classification number: H01L22/34 H01L27/0886

    Abstract: A test pattern of a semiconductor device is provided, which includes first and second fins formed to project from a substrate and arranged to be spaced apart from each other, first and second gate structures formed to cross the first and second fins, respectively, a first source region and a first drain region arranged on the first fin on one side and the other side of the first gate structure, a second source region and a second drain region arranged on the second fin on one side and the other side of the second gate structure, a first conductive pattern connected to the first and second drain regions to apply a first voltage to the first and second drain regions and a second conductive pattern connecting the first source region and the second gate structure to each other.

    Abstract translation: 提供了一种半导体器件的测试图案,其包括形成为从衬底突出并布置成彼此间隔开的第一和第二鳍片,分别形成为跨越第一和第二鳍片的第一和第二栅极结构,第一和第二鳍片 源极区域和布置在第一鳍片的第一栅极结构的一侧和另一侧上的第一漏极区域,在第二栅极的一侧和另一侧上布置在第二鳍片上的第二源极区域和第二漏极区域 结构,连接到第一和第二漏极区域以将第一电压施加到第一和第二漏极区域的第一导电图案以及将第一源极区域和第二栅极结构彼此连接的第二导电图案。

    Semiconductor device comprising capacitor and method of manufacturing the same
    9.
    发明授权
    Semiconductor device comprising capacitor and method of manufacturing the same 有权
    包括电容器的半导体器件及其制造方法

    公开(公告)号:US09190402B2

    公开(公告)日:2015-11-17

    申请号:US14245079

    申请日:2014-04-04

    Abstract: A semiconductor device includes an interlayer dielectric layer on a substrate, the interlayer dielectric layer having an upper surface, a lower plug extending down into the interlayer dielectric layer from the upper surface of the interlayer dielectric layer, the lower plug having an upper surface, a first dielectric layer pattern on the upper surface of the lower plug, at least a portion of the first dielectric layer pattern being directly connected to the upper surface of the lower plug, a first metal electrode pattern on the first dielectric layer pattern, a first upper plug electrically connected to the first metal electrode pattern, and a second upper plug on the lower plug, the second upper plug being spaced apart from the first upper plug.

    Abstract translation: 半导体器件包括在衬底上的层间电介质层,层间绝缘层具有上表面,下电极从层间电介质层的上表面向下延伸到层间电介质层中,下插塞具有上表面, 第一电介质层图案在下塞子的上表面上,第一介电层图案的至少一部分直接连接到下塞子的上表面,第一介电层图案上的第一金属电极图案,第一上层 电插头与第一金属电极图形电连接,第二上插头位于下插头上,第二上插头与第一上插头间隔开。

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