公开(公告)号：US20140143518A1

公开(公告)日：2014-05-22

申请号：US14082938

申请日：2013-11-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： DONG-WOO KIM ,  Sang-Hwa Jin ,  Sang-Jong Kim

IPC: G06F12/10

CPC classification number: G06F12/10 ,  G06F12/0223 ,  G06F2212/205

Abstract: A memory system comprises a central processing unit. A memory management unit receives a virtual address from the central processing unit. The memory management unit converts the virtual address into a physical address. A main memory is assessed based on the physical address. The main memory stores data used the central processing unit. The main memory includes a first area including a non-volatile memory. First file data having a first characteristic is included in the first area of the main memory. The main memory includes a second area including a volatile memory. Second file data having a second characteristic different from the first characteristic is included in the second area of the main memory. A management table manages only the first area of the first and second areas of the main memory.

Abstract translation: 存储器系统包括中央处理单元。 存储器管理单元从中央处理单元接收虚拟地址。 存储器管理单元将虚拟地址转换成物理地址。 主存储器根据物理地址进行评估。 主存储器存储使用中央处理单元的数据。 主存储器包括包括非易失性存储器的第一区域。 具有第一特性的第一文件数据被包括在主存储器的第一区域中。 主存储器包括包括易失性存储器的第二区域。 具有与第一特性不同的第二特征的第二文件数据被包括在主存储器的第二区域中。 管理表仅管理主存储器的第一和第二区域的第一区域。

公开(公告)号：US09362220B2

公开(公告)日：2016-06-07

申请号：US14587291

申请日：2014-12-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Jong Kim ,  Jae-Hyeon Park ,  Sung-Hoon Bae ,  Jong-Wan Ma

IPC: H01L23/60 ,  H01L23/50 ,  H01L27/02 ,  H01L21/8234 ,  H01L23/00

CPC classification number: H01L23/50 ,  H01L21/823475 ,  H01L23/60 ,  H01L24/05 ,  H01L27/0292 ,  H01L2924/01019 ,  H01L2924/01021

Abstract: A semiconductor device, including a substrate having an active region defined therein, a plurality of bit lines extending on the substrate in a first direction, a plurality of interconnection lines extending on the substrate in a second direction, a pad electrically connected to the plurality of interconnection lines and configured to apply an external voltage, a plurality of metal contacts electrically connecting the interconnection lines and the plurality of bit lines, and a plurality of bit line contacts that are in contact with the active region and electrically connect the plurality of bit lines and the active region, wherein a size of at least some of the bit line contacts and/or at least some of the metal contacts vary based on a distance of the respective bit line contact or the metal contact from the pad.