公开(公告)号：US20190181848A1

公开(公告)日：2019-06-13

申请号：US16204520

申请日：2018-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Kyeom KIM ,  Won-Joo Yun ,  SukYong Kang ,  Ho-Jun Chang

IPC: H03K5/156 ,  H03L7/081 ,  H03L7/089 ,  G11C7/22

Abstract: A delay locked loop circuit includes a duty detector configured to detect a duty cycle of a clock signal, and to determine whether to perform a coarse duty cycle correction based on the detected duty, and a delay locked loop core. The delay locked loop core is configured to selectively perform the coarse duty cycle correction for the clock signal according to the determination of the duty detector, perform a coarse lock for the clock signal during a first time period different from a second time period in which the coarse duty cycle correction is performed, and perform a fine duty cycle correction and a fine lock for the clock signal.