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    MEMORY DEVICE
    2.
    发明申请
    MEMORY DEVICE 审中-公开

    公开(公告)号：US20190271742A1

    公开(公告)日：2019-09-05

    申请号：US16169107

    申请日：2018-10-24

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyunui Lee ,  Hye-Seung Yu ,  Won-Joo Yun

    IPC: G01R31/317 ,  G01R31/3177 ,  G11C29/02

    Abstract: A semiconductor memory device includes first bumps positioned along a first direction; second bumps positioned in parallel to the first bumps along the first direction; first registers connected with the first bumps; and second registers connected with the second bumps. The first registers and the second registers are sequentially connected and form a shift register.

    Electronic device having a delay locked loop, and memory device having the same
    7.
    发明授权
    Electronic device having a delay locked loop, and memory device having the same 有权

    公开(公告)号：US09654093B2

    公开(公告)日：2017-05-16

    申请号：US14955051

    申请日：2015-12-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Won-Joo Yun ,  Yong Shim

    IPC: H03L7/06 ,  H03K7/08 ,  H03L7/085 ,  H03K5/156

    CPC classification number: H03K7/08 ,  H03K5/1565 ,  H03L7/085

    Abstract: An electronic device includes a first duty cycle correction circuit, a delay line, a second duty cycle correction circuit, and a delay control circuit. The first duty cycle correction circuit is configured to detect a duty cycle error of a clock signal by performing time-to-digital conversion on the clock signal, and to generate a corrected clock signal by adjusting a duty cycle of the clock signal based on the duty cycle error of the clock signal. The delay line is configured to generate a delayed corrected clock signal by delaying the corrected clock signal based on a delay control code The second duty cycle correction circuit is configured to detect a duty cycle error of a first output clock signal received through a feedback loop, and to generate a second output clock signal by adjusting duty cycle of the delayed corrected clock signal based on the duty cycle error of the first output clock signal. The delay control circuit is configured to generate the delay control code based on the clock signal and the first output clock signal.

    Duty cycle error detection device and duty cycle correction device having the same
    8.
    发明授权
    Duty cycle error detection device and duty cycle correction device having the same 有权
    占空比误差检测装置和占空比校正装置

    公开(公告)号：US09501041B2

    公开(公告)日：2016-11-22

    申请号：US14699290

    申请日：2015-04-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yong Shim ,  Won-Joo Yun

    IPC: H03K3/017 ,  G04F10/00 ,  H03K5/156 ,  H03K5/135

    CPC classification number: G04F10/005 ,  H03K5/135 ,  H03K5/1565

    Abstract: In a duty cycle error detection device, a first digital code generator is configured to generate high and low codes corresponding to a lengths of high level low level periods, respectively, of a clock signal, generate a sign signal representing the longer period between the high level period and the low level period, and output one of the high and low digital codes corresponding to the shorter period as a first digital code. A clock delay circuit is configured to generate a delay clock signal by delaying the clock signal for a time corresponding to the first digital code, and a second digital code generator is configured to generate a duty error digital code corresponding to a length from a start of the longer period of the delay clock signal to an end of the longer period of the clock signal based on the sign signal.

    Abstract translation: 在占空比误差检测装置中，第一数字码发生器被配置为分别产生对应于时钟信号的高电平低电平时段的长度的高和低码，产生表示较高时段之间的较长周期的符号信号 电平周期和低电平周期，并将对应于较短周期的高数字代码和低数字代码之一作为第一数字代码输出。 时钟延迟电路被配置为通过将时钟信号延迟与第一数字代码相对应的时间来产生延迟时钟信号，并且第二数字代码发生器被配置为生成对应于从开始的时间的长度的占空误差数字代码 基于符号信号，延迟时钟信号的较长周期延迟到时钟信号的较长周期的结束。

    Input buffer and memory device including the same
    10.
    发明授权
    Input buffer and memory device including the same 有权
    输入缓冲器和包含相同的存储器件

    公开(公告)号：US09214202B2

    公开(公告)日：2015-12-15

    申请号：US14644339

    申请日：2015-03-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yong Shim ,  Seung-Jun Bae ,  Won-Joo Yun

    IPC: G11C16/04 ,  G11C7/10

    CPC classification number: G11C7/1084 ,  G11C7/1054

    Abstract: An input buffer includes a first buffer, a feedback circuit and a second buffer circuit. The feedback circuit includes a feedback resistor and a feedback inverter. The first buffer may be configured to output an amplification signal to an output node of the first buffer based on an input signal. The feedback circuit connected to the output node of the first buffer may be configured to control the amplification signal. The second buffer circuit may be configured to output a buffer output signal by buffering the amplification signal. The feedback resistor may receive the amplification signal from the output node of the first buffer and provide a feedback signal to a feedback node. The feedback inverter is connected between the feedback node and the output node. The feedback inverter may be configured to control the amplification signal based on the feedback signal.

    Abstract translation: 输入缓冲器包括第一缓冲器，反馈电路和第二缓冲电路。 反馈电路包括反馈电阻和反馈反馈器。 第一缓冲器可以被配置为基于输入信号将放大信号输出到第一缓冲器的输出节点。 连接到第一缓冲器的输出节点的反馈电路可以被配置为控制放大信号。 第二缓冲电路可以被配置为通过缓冲放大信号来输出缓冲器输出信号。 反馈电阻器可以从第一缓冲器的输出节点接收放大信号，并向反馈节点提供反馈信号。 反馈逆变器连接在反馈节点和输出节点之间。 反馈反相器可以被配置为基于反馈信号来控制放大信号。

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