公开(公告)号：US20170125085A1

公开(公告)日：2017-05-04

申请号：US15334380

申请日：2016-10-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Se-Young KIM ,  Junbae KIM

IPC: G11C11/4078 ,  H01L27/02 ,  H01L27/108 ,  H02H9/04

CPC classification number: G11C11/4078 ,  G11C5/14 ,  G11C11/4074 ,  H01L27/0266 ,  H01L27/0285 ,  H01L27/0288 ,  H01L27/10897 ,  H02H9/046

Abstract: Disclosed is an integrated protecting circuit, which detects ESD and EOS pulses to prevent an over-voltage from being applied to a semiconductor device. The integrated protecting circuit includes a first detector configured to detect an occurrence of an electrical over-stress between a first node to which a first voltage is applied and a second node to which a second voltage is applied, a second detector configured to detect an occurrence of an electrostatic discharge between the first and second nodes, a determination circuit configured to receive separate outputs of the first and second detectors at the same time and to generate a control signal, and a clamping device configured to perform a turn on/off operation in response to the control signal such that a voltage between the first and second nodes is clamped into a constant voltage.