公开(公告)号：US20220037306A1

公开(公告)日：2022-02-03

申请号：US17190689

申请日：2021-03-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seho YOU ,  Kyounglim SUK

IPC: H01L25/18 ,  H01L23/498 ,  H01L23/522 ,  H01L23/31 ,  H01L23/00 ,  H01L23/48 ,  H01L23/66

Abstract: A semiconductor package is provided. The semiconductor package comprising a first redistribution structure comprising a first redistribution pattern; a first semiconductor chip on the first redistribution structure, the first semiconductor chip comprising a semiconductor substrate comprising a first surface and a second surface, a first back end of line (BEOL) structure on the first surface of the semiconductor substrate and comprising a first interconnect pattern, and a second BEOL structure on the second surface of the semiconductor substrate and comprising a second interconnect pattern; a molding layer covering a sidewall of the first semiconductor chip; a second redistribution structure on the first semiconductor chip and the molding layer and comprising a second redistribution pattern electrically connected to the second interconnect pattern.

公开(公告)号：US20230253392A1

公开(公告)日：2023-08-10

申请号：US18301420

申请日：2023-04-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seho YOU ,  Kyounglim SUK

IPC: H01L25/18 ,  H01L23/498 ,  H01L23/522 ,  H01L23/31 ,  H01L23/00 ,  H01L23/48 ,  H01L23/66

CPC classification number: H01L25/18 ,  H01L23/49822 ,  H01L23/5226 ,  H01L23/3128 ,  H01L24/20 ,  H01L23/481 ,  H01L23/66 ,  H01L23/49811 ,  H01L24/16 ,  H01L2223/6677 ,  H01L2224/16227

Abstract: A semiconductor package is provided. The semiconductor package comprising a first redistribution structure comprising a first redistribution pattern; a first semiconductor chip on the first redistribution structure, the first semiconductor chip comprising a semiconductor substrate comprising a first surface and a second surface, a first back end of line (BEOL) structure on the first surface of the semiconductor substrate and comprising a first interconnect pattern, and a second BEOL structure on the second surface of the semiconductor substrate and comprising a second interconnect pattern; a molding layer covering a sidewall of the first semiconductor chip; a second redistribution structure on the first semiconductor chip and the molding layer and comprising a second redistribution pattern electrically connected to the second interconnect pattern.