公开(公告)号：US20240069093A1

公开(公告)日：2024-02-29

申请号：US18174865

申请日：2023-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sehyun Hwang ,  Jongmin Lee ,  Joongwon Shin ,  Jimin Choi

IPC: G01R31/28 ,  H01L23/00 ,  H01L23/50 ,  H01L23/528 ,  H10B80/00

CPC classification number: G01R31/2884 ,  H01L23/50 ,  H01L23/528 ,  H01L24/05 ,  H10B80/00 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/0557 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2924/1431 ,  H01L2924/14361

Abstract: Provided are a semiconductor chip with a reduced thickness and improved reliability, and a semiconductor package including the semiconductor chip. The semiconductor chip includes a semiconductor substrate, an integrated device layer on the semiconductor substrate, a multi-wiring layer on the integrated device layer, and a pad metal layer of a plurality of pad metal layers on the multi-wiring layer, and having test pads defined therein. The pad metal layers extend in a first direction parallel to a top surface of the semiconductor substrate or in a second direction perpendicular to the first direction. A test pad is a central portion of the pad metal layer and, and an outer portion of the pad metal layer excluding the test pad overlaps the wires in a third direction perpendicular to the top surface of the semiconductor substrate.