公开(公告)号：US10132865B2

公开(公告)日：2018-11-20

申请号：US15170940

申请日：2016-06-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seon-kyoo Lee ,  Jeong-don Ihm ,  Byung-hoon Jeong ,  Dae-woon Kang ,  Tae-sung Lee ,  Sang-lok Kim

IPC: G01R31/28 ,  G01R31/3183 ,  G01R31/317

Abstract: A semiconductor chip, a test system, and a method of testing the semiconductor chip. The semiconductor chip includes a pulse generator configured to generate a test pulse in response to a test request; a logic chain comprising a plurality of logic devices serially connected to each other and transferring the test pulse sequentially; and a detector configured to detect a logic level of an output signal of each of the logic devices and output a detection result indicating a degree of an inter-symbol interference (ISI).

公开(公告)号：US10439632B2

公开(公告)日：2019-10-08

申请号：US16191367

申请日：2018-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Anil Kavala ,  Seon-kyoo Lee ,  Byung-hoon Jeong ,  Jeong-don Ihm ,  Young-don Choi

IPC: G05F3/08 ,  H03M1/78 ,  G11C5/14

Abstract: A semiconductor device includes a reference voltage generator configured to output a reference voltage. The reference voltage generator includes a boosting code circuit and a first digital-analog converter (DAC). The boosting code circuit includes a first boosting pulse generator configured to generate a first boosting pulse and a first boosting code controller configured to output a first boosting code based on a reference code and the first boosting pulse. The first DAC is configured to output the reference voltage by converting the first boosting code. The first boosting code has a first code value different from the reference code when the first boosting pulse has a first logic level, and the first boosting code has the same value as the reference code when the first boosting pulse has a second logic level opposite to the first logic level.