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公开(公告)号：US10600454B2
公开(公告)日：2020-03-24
申请号：US15975266
申请日：2018-05-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dong-su Jang , Man-jae Yang , Jeong-don Ihm , Go-eun Jung , Byung-hoon Jeong , Young-don Choi
IPC: G11C7/00 , G11C7/10 , G11C11/4096 , G11C7/22 , G11C11/4076 , G11C16/26 , G11C5/06
Abstract: A non-volatile memory device includes a serial pipeline structure connected to an output stage of a First In, First Out (FIFO) memory. The FIFO memory is configured to store data transmitted through a data path having a wave pipeline structure based on a plurality of FIFO input clock signals and output the stored data based on a plurality of FIFO output clock signals. A serializer is configured to output data to an input/output pad based on a select clock signal. The serial pipeline structure is connected between the FIFO memory and the serializer and configured to compensate for a phase difference between the data output from the FIFO memory and the select clock signal.
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公开(公告)号：US11257531B2
公开(公告)日：2022-02-22
申请号：US17159516
申请日：2021-01-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jung-june Park , Jeong-don Ihm , Byung-hoon Jeong , Eun-ji Kim , Ji-yeon Shin , Young-don Choi
Abstract: Provided is a nonvolatile memory including a clock pin configured to receive an external clock signal during a duty correction circuit training period; a plurality of memory chips configured to perform a duty correction operation on an internal clock signal based on the external clock signal, the plurality of memory chips configured to perform the duty correction operation in parallel during the training period; and an input/output pin commonly connected to the plurality of memory chips, wherein each of the plurality of memory chips includes: a duty correction circuit (DCC) configured to perform the duty correction operation on the internal clock signal; and an output buffer connected between an output terminal of the DCC and the input/output pin.
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公开(公告)号：US10439632B2
公开(公告)日：2019-10-08
申请号：US16191367
申请日：2018-11-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Anil Kavala , Seon-kyoo Lee , Byung-hoon Jeong , Jeong-don Ihm , Young-don Choi
Abstract: A semiconductor device includes a reference voltage generator configured to output a reference voltage. The reference voltage generator includes a boosting code circuit and a first digital-analog converter (DAC). The boosting code circuit includes a first boosting pulse generator configured to generate a first boosting pulse and a first boosting code controller configured to output a first boosting code based on a reference code and the first boosting pulse. The first DAC is configured to output the reference voltage by converting the first boosting code. The first boosting code has a first code value different from the reference code when the first boosting pulse has a first logic level, and the first boosting code has the same value as the reference code when the first boosting pulse has a second logic level opposite to the first logic level.
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Patent Agency Ranking
4.发明申请公开(公告)号：US20200066317A1
公开(公告)日：2020-02-27
申请号：US16668685
申请日：2019-10-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jung-june Park , Jeong-don Ihm , Byung-hoon Jeong , Eun-ji Kim , Ji-yeon Shin , Young-don Choi
Abstract: Provided is a nonvolatile memory including a clock pin configured to receive an external clock signal during a duty correction circuit training period; a plurality of memory chips configured to perform a duty correction operation on an internal clock signal based on the external clock signal, the plurality of memory chips configured to perform the duty correction operation in parallel during the training period; and an input/output pin commonly connected to the plurality of memory chips, wherein each of the plurality of memory chips includes: a duty correction circuit (DCC) configured to perform the duty correction operation on the internal clock signal; and an output buffer connected between an output terminal of the DCC and the input/output pin.
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公开(公告)号：US10482935B2
公开(公告)日：2019-11-19
申请号：US15982431
申请日：2018-05-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jung-june Park , Jeong-Don Ihm , Byung-hoon Jeong , Eun-ji Kim , Ji-yeon Shin , Young-don Choi
Abstract: Provided is a nonvolatile memory including a clock pin configured to receive an external clock signal during a duty correction circuit training period; a plurality of memory chips configured to perform a duty correction operation on an internal clock signal based on the external clock signal, the plurality of memory chips configured to perform the duty correction operation in parallel during the training period; and an input/output pin commonly connected to the plurality of memory chips, wherein each of the plurality of memory chips includes: a duty correction circuit (DCC) configured to perform the duty correction operation on the internal clock signal; and an output buffer connected between an output terminal of the DCC and the input/output pin.
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6.发明申请公开(公告)号：US20180350414A1
公开(公告)日：2018-12-06
申请号：US15982431
申请日：2018-05-17
Applicant: Samsung Electronics Co, Ltd
Inventor： Jung-june PARK , Jeong-Don Ihm , Byung-hoon Jeong , Eun-ji Kim , Ji-yeon Shin , Young-don Choi
CPC classification number: G11C7/222 , G11C7/1057 , G11C7/1066 , G11C16/26 , G11C16/32 , G11C2207/2254 , H03K3/017 , H03K5/1565
Abstract: Provided is a nonvolatile memory including a clock pin configured to receive an external clock signal during a duty correction circuit training period; a plurality of memory chips configured to perform a duty correction operation on an internal clock signal based on the external clock signal, the plurality of memory chips configured to perform the duty correction operation in parallel during the training period; and an input/output pin commonly connected to the plurality of memory chips, wherein each of the plurality of memory chips includes: a duty correction circuit (DCC) configured to perform the duty correction operation on the internal clock signal; and an output buffer connected between an output terminal of the DCC and the input/output pin.
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公开(公告)号：US20210151089A1
公开(公告)日：2021-05-20
申请号：US17159516
申请日：2021-01-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jung-june Park , Jeong-don Ihm , Byung-hoon Jeong , Eun-ji Kim , Ji-yeon Shin , Young-don Choi
Abstract: Provided is a nonvolatile memory including a clock pin configured to receive an external clock signal during a duty correction circuit training period; a plurality of memory chips configured to perform a duty correction operation on an internal clock signal based on the external clock signal, the plurality of memory chips configured to perform the duty correction operation in parallel during the training period; and an input/output pin commonly connected to the plurality of memory chips, wherein each of the plurality of memory chips includes: a duty correction circuit (DCC) configured to perform the duty correction operation on the internal clock signal; and an output buffer connected between an output terminal of the DCC and the input/output pin.
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公开(公告)号：US10937474B2
公开(公告)日：2021-03-02
申请号：US16668685
申请日：2019-10-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jung-june Park , Jeong-don Ihm , Byung-hoon Jeong , Eun-ji Kim , Ji-yeon Shin , Young-don Choi
Abstract: Provided is a nonvolatile memory including a clock pin configured to receive an external clock signal during a duty correction circuit training period; a plurality of memory chips configured to perform a duty correction operation on an internal clock signal based on the external clock signal, the plurality of memory chips configured to perform the duty correction operation in parallel during the training period; and an input/output pin commonly connected to the plurality of memory chips, wherein each of the plurality of memory chips includes: a duty correction circuit (DCC) configured to perform the duty correction operation on the internal clock signal; and an output buffer connected between an output terminal of the DCC and the input/output pin.
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