公开(公告)号：US11049815B2

公开(公告)日：2021-06-29

申请号：US16584027

申请日：2019-09-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jooyoung Choi ,  Taewook Kim ,  Byungho Kim ,  Sangseok Hong ,  Jaehoon Choi ,  Seongjin Shin

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367

Abstract: A semiconductor package includes a connection structure having first and second surfaces opposing each other and including a redistribution layer. A semiconductor chip is disposed on the first surface of the connection structure and has connection pads connected to the redistribution layer. An encapsulant is disposed on the first surface of the connection structure and covers the semiconductor chip. A support pattern is disposed on a portion of an upper surface of the encapsulant. A heat dissipation bonding material has a portion embedded in the encapsulant in a region overlapping the semiconductor chip and extends to the upper surface of the encapsulant so as to cover the support pattern. A heat dissipation element is bonded to the upper surface of the encapsulant by the heat dissipation bonding material.

公开(公告)号：US20220068814A1

公开(公告)日：2022-03-03

申请号：US17237223

申请日：2021-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byungho Kim ,  Seongjin Shin

IPC: H01L23/528 ,  H01L23/522

Abstract: A semiconductor package includes a substrate, at least one semiconductor chip arranged in the substrate and having chip pads, and a redistribution wiring layer covering a lower surface of the substrate and including first and second redistribution wirings and dummy patterns, the first and second redistribution wirings being stacked in at least two levels and connected to the chip pads. The first and second redistribution wirings are arranged in a redistribution region of the redistribution wiring layer, and the dummy patterns extend in an outer region outside the redistribution region to partially cover corner portions of the redistribution wiring layer, respectively.

公开(公告)号：US20220059437A1

公开(公告)日：2022-02-24

申请号：US17195774

申请日：2021-03-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byungho Kim ,  Seongjin Shin

IPC: H01L23/495 ,  H01L23/00 ,  H01L25/065 ,  H01L23/538 ,  H01L23/31

Abstract: A semiconductor package includes a package substrate including a redistribution layer; a semiconductor chip disposed on the package substrate and electrically connected to the redistribution layer; a wiring structure disposed on the semiconductor chip and having an upper surface on which pads are arranged; a vertical connection structure disposed between the package substrate and the wiring structure and electrically connecting the redistribution layer and the pads; and a passivation layer disposed on the wiring structure and having openings partially exposing a region of each of the pads. The pads include a first pad adjacent to a corner of the wiring structure, and a second pad closer to a center of the wiring structure than the first pad. A first width of the first pad is greater than a second width of the second pad. A contact layer is disposed in the opening on the first pad.

公开(公告)号：US11594488B2

公开(公告)日：2023-02-28

申请号：US17237223

申请日：2021-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byungho Kim ,  Seongjin Shin

IPC: H01L23/528 ,  H01L23/522

Abstract: A semiconductor package includes a substrate, at least one semiconductor chip arranged in the substrate and having chip pads, and a redistribution wiring layer covering a lower surface of the substrate and including first and second redistribution wirings and dummy patterns, the first and second redistribution wirings being stacked in at least two levels and connected to the chip pads. The first and second redistribution wirings are arranged in a redistribution region of the redistribution wiring layer, and the dummy patterns extend in an outer region outside the redistribution region to partially cover corner portions of the redistribution wiring layer, respectively.

公开(公告)号：US11854948B2

公开(公告)日：2023-12-26

申请号：US17195774

申请日：2021-03-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byungho Kim ,  Seongjin Shin

IPC: H01L23/31 ,  H01L23/495 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/4952 ,  H01L23/31 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/14 ,  H01L25/0657

Abstract: A semiconductor package includes a package substrate including a redistribution layer; a semiconductor chip disposed on the package substrate and electrically connected to the redistribution layer; a wiring structure disposed on the semiconductor chip and having an upper surface on which pads are arranged; a vertical connection structure disposed between the package substrate and the wiring structure and electrically connecting the redistribution layer and the pads; and a passivation layer disposed on the wiring structure and having openings partially exposing a region of each of the pads. The pads include a first pad adjacent to a corner of the wiring structure, and a second pad closer to a center of the wiring structure than the first pad. A first width of the first pad is greater than a second width of the second pad. A contact layer is disposed in the opening on the first pad.