公开(公告)号：US11854948B2

公开(公告)日：2023-12-26

申请号：US17195774

申请日：2021-03-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byungho Kim ,  Seongjin Shin

IPC: H01L23/31 ,  H01L23/495 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/4952 ,  H01L23/31 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/14 ,  H01L25/0657

Abstract: A semiconductor package includes a package substrate including a redistribution layer; a semiconductor chip disposed on the package substrate and electrically connected to the redistribution layer; a wiring structure disposed on the semiconductor chip and having an upper surface on which pads are arranged; a vertical connection structure disposed between the package substrate and the wiring structure and electrically connecting the redistribution layer and the pads; and a passivation layer disposed on the wiring structure and having openings partially exposing a region of each of the pads. The pads include a first pad adjacent to a corner of the wiring structure, and a second pad closer to a center of the wiring structure than the first pad. A first width of the first pad is greater than a second width of the second pad. A contact layer is disposed in the opening on the first pad.

公开(公告)号：US11594488B2

公开(公告)日：2023-02-28

申请号：US17237223

申请日：2021-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byungho Kim ,  Seongjin Shin

IPC: H01L23/528 ,  H01L23/522

Abstract: A semiconductor package includes a substrate, at least one semiconductor chip arranged in the substrate and having chip pads, and a redistribution wiring layer covering a lower surface of the substrate and including first and second redistribution wirings and dummy patterns, the first and second redistribution wirings being stacked in at least two levels and connected to the chip pads. The first and second redistribution wirings are arranged in a redistribution region of the redistribution wiring layer, and the dummy patterns extend in an outer region outside the redistribution region to partially cover corner portions of the redistribution wiring layer, respectively.

公开(公告)号：US11121069B2

公开(公告)日：2021-09-14

申请号：US16580480

申请日：2019-09-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehoon Choi ,  Doohwan Lee ,  Byungho Kim ,  Jooyoung Choi

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/13 ,  H01L21/48

Abstract: A semiconductor package includes a semiconductor chip including a connection pad disposed on an active surface of the semiconductor chip, a passivation layer disposed on the connection pad and the active surface and having an opening exposing at least a portion of the connection pad, and a capping pad covering the connection pad exposed to the opening; an encapsulant covering at least a portion of the semiconductor chip; and a connection structure disposed on the active surface of the semiconductor chip and including a connection via connected to the capping pad and a redistribution layer connected to the connection via, wherein the capping pad includes: a central portion disposed in the opening, and a peripheral portion extending from the central portion onto the passivation layer, and having a crystal grain having a size different from that of the crystal grain of the central portion.

公开(公告)号：US20240021531A1

公开(公告)日：2024-01-18

申请号：US18191212

申请日：2023-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongkoon Lee ,  Youngchan Ko ,  Byungho Kim

IPC: H01L23/538 ,  H01L23/498 ,  H10B80/00

CPC classification number: H01L23/5386 ,  H01L23/5383 ,  H01L23/5381 ,  H01L23/49816 ,  H10B80/00 ,  H01L2224/16227 ,  H01L24/16

Abstract: A semiconductor package includes a substrate including a first redistribution member including a first surface and a second surface, and including a first redistribution layer, an interconnection chip below the second surface and including an interconnection circuit electrically connected to the first redistribution layer, a via structure around the interconnection chip and electrically connected to the first redistribution layer, an encapsulant between the second surface and the interconnection chip and the via structure, a first pillar extending through the encapsulant to electrically connect the first redistribution layer and the interconnection circuit, a second pillar extending through the encapsulant to electrically connect the first redistribution layer and the via structure, and connection bumps below the interconnection chip and the via structure, and first and second chip structures on the first surface of the first redistribution member and electrically connected to the first redistribution layer. The first pillar and the second pillar have different shapes.

公开(公告)号：US20240014197A1

公开(公告)日：2024-01-11

申请号：US18298702

申请日：2023-04-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yongkoon Lee ,  Youngchan Ko ,  Byungho Kim

IPC: H01L25/18 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01L21/768 ,  H10B80/00

CPC classification number: H01L25/18 ,  H01L23/3121 ,  H01L24/13 ,  H01L24/16 ,  H01L23/49827 ,  H01L23/49833 ,  H01L21/76871 ,  H10B80/00 ,  H01L24/11 ,  H01L2224/13025 ,  H01L2224/16227 ,  H01L2924/3511 ,  H01L2224/11436

Abstract: A semiconductor package includes: a substrate including a redistribution member having a first surface and a second surface, opposing each other, and including pad structures disposed on the first surface and a redistribution layer electrically connected to the pad structures, an interconnect chip disposed on the second surface of the redistribution member and including an interconnect circuit electrically connected to the redistribution layer, a via structure disposed around the interconnect chip and electrically connected to the redistribution layer, an encapsulant encapsulating at least a portion of each of the interconnect chip and the via structure, and bump structures disposed on the encapsulant; and a first chip structure and a second chip structure disposed on the first surface of the redistribution member and electrically connected to the pad structures.

公开(公告)号：US11049815B2

公开(公告)日：2021-06-29

申请号：US16584027

申请日：2019-09-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jooyoung Choi ,  Taewook Kim ,  Byungho Kim ,  Sangseok Hong ,  Jaehoon Choi ,  Seongjin Shin

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367

Abstract: A semiconductor package includes a connection structure having first and second surfaces opposing each other and including a redistribution layer. A semiconductor chip is disposed on the first surface of the connection structure and has connection pads connected to the redistribution layer. An encapsulant is disposed on the first surface of the connection structure and covers the semiconductor chip. A support pattern is disposed on a portion of an upper surface of the encapsulant. A heat dissipation bonding material has a portion embedded in the encapsulant in a region overlapping the semiconductor chip and extends to the upper surface of the encapsulant so as to cover the support pattern. A heat dissipation element is bonded to the upper surface of the encapsulant by the heat dissipation bonding material.

公开(公告)号：US20240063070A1

公开(公告)日：2024-02-22

申请号：US18231363

申请日：2023-08-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngchan Ko ,  Byungho Kim ,  Yongkoon Lee

IPC: H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L21/56

CPC classification number: H01L23/3121 ,  H01L24/16 ,  H01L25/0657 ,  H01L21/565 ,  H01L2224/16225 ,  H01L2225/06541 ,  H01L2924/3511

Abstract: A method of manufacturing a semiconductor package, the method including forming a first solder ball on a surface of a redistribution layer, forming a preliminary molding layer on the surface of the redistribution layer and the first solder ball, exposing the first solder ball by grinding the preliminary molding layer and the first solder ball, and forming a second solder ball by reflowing the first solder ball, wherein the second solder ball is spaced apart from the molding layer, in a horizontal direction.

公开(公告)号：US20220068814A1

公开(公告)日：2022-03-03

申请号：US17237223

申请日：2021-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byungho Kim ,  Seongjin Shin

IPC: H01L23/528 ,  H01L23/522

Abstract: A semiconductor package includes a substrate, at least one semiconductor chip arranged in the substrate and having chip pads, and a redistribution wiring layer covering a lower surface of the substrate and including first and second redistribution wirings and dummy patterns, the first and second redistribution wirings being stacked in at least two levels and connected to the chip pads. The first and second redistribution wirings are arranged in a redistribution region of the redistribution wiring layer, and the dummy patterns extend in an outer region outside the redistribution region to partially cover corner portions of the redistribution wiring layer, respectively.

公开(公告)号：US20220059437A1

公开(公告)日：2022-02-24

申请号：US17195774

申请日：2021-03-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byungho Kim ,  Seongjin Shin

IPC: H01L23/495 ,  H01L23/00 ,  H01L25/065 ,  H01L23/538 ,  H01L23/31

Abstract: A semiconductor package includes a package substrate including a redistribution layer; a semiconductor chip disposed on the package substrate and electrically connected to the redistribution layer; a wiring structure disposed on the semiconductor chip and having an upper surface on which pads are arranged; a vertical connection structure disposed between the package substrate and the wiring structure and electrically connecting the redistribution layer and the pads; and a passivation layer disposed on the wiring structure and having openings partially exposing a region of each of the pads. The pads include a first pad adjacent to a corner of the wiring structure, and a second pad closer to a center of the wiring structure than the first pad. A first width of the first pad is greater than a second width of the second pad. A contact layer is disposed in the opening on the first pad.

公开(公告)号：US20200152565A1

公开(公告)日：2020-05-14

申请号：US16580480

申请日：2019-09-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehoon Choi ,  Doohwan Lee ,  Byungho Kim ,  Jooyoung Choi

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/13 ,  H01L21/48

Abstract: A semiconductor package includes a semiconductor chip including a connection pad disposed on an active surface of the semiconductor chip, a passivation layer disposed on the connection pad and the active surface and having an opening exposing at least a portion of the connection pad, and a capping pad covering the connection pad exposed to the opening; an encapsulant covering at least a portion of the semiconductor chip; and a connection structure disposed on the active surface of the semiconductor chip and including a connection via connected to the capping pad and a redistribution layer connected to the connection via, wherein the capping pad includes: a central portion disposed in the opening, and a peripheral portion extending from the central portion onto the passivation layer, and having a crystal grain having a size different from that of the crystal grain of the central portion.