公开(公告)号：US20220113909A1

公开(公告)日：2022-04-14

申请号：US17375328

申请日：2021-07-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myungsub SHIN ,  Sungho SEO ,  Seongyong JANG ,  Haesung JUNG

IPC: G06F3/06

Abstract: An electronic device may include a host device and a storage device which are connected in a universal flash storage standard, wherein the host device may include processing circuitry configured to process a submission queue (SQ) and a completion queue (CQ), wherein the SQ is a processing standby line of a command, and the CQ is a processing standby line of a response received from the storage device, transmit the command to the storage device, store a host command credit in a host command register, the host command credit indicating an estimated command accommodation limit of the storage device, store the response in a response slot, and store a host response credit in a host command register, the host command credit indicating a limit of the response slot.

公开(公告)号：US20240370196A1

公开(公告)日：2024-11-07

申请号：US18380945

申请日：2023-10-17

Applicant: SAMSUNG ELECTRONICS CO, LTD.

Inventor： Youngmin LEE ,  Seongheum BAIK ,  Myungsub SHIN ,  Seongyong JANG ,  Gyuseok CHOE

IPC: G06F3/06

Abstract: Disclosed is a storage device which includes a nonvolatile memory device that includes a plurality of erase units each including a plurality of memory cells, and a memory controller. Based on an open zone request received from an external host device, the memory controller allocates a zone to at least one erase unit among the plurality of erase units and permits only a sequential write with respect to the zone. The memory controller generates a map table mapping sequential logical addresses of data written in the zone to sequential physical addresses. Based on a partial invalidation request received from the external host device, the memory controller manages data corresponding to the partial invalidation request from among the data written in the zone as invalid data while maintaining the map table.

公开(公告)号：US20240272816A1

公开(公告)日：2024-08-15

申请号：US18497087

申请日：2023-10-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gyuseok CHOE ,  Seongheum BAIK ,  Myungsub SHIN ,  Youngmin LEE ,  Seongyong JANG

IPC: G06F3/06

CPC classification number: G06F3/0631 ,  G06F3/0604 ,  G06F3/0647 ,  G06F3/0656 ,  G06F3/0679

Abstract: A storage device and an operating method of the same are disclosed. The storage device includes a memory controller and a non-volatile memory, wherein the memory controller is configured to calculate a number of zones, which are spaces allocated to logical addresses, based on a cell area size of first storage areas of the non-volatile memory, and provide the number of zones to a host, is configured to generate multiple zones of a number within the calculated number of zones, and to map a logical address of each zone to a physical address of at least one of the first storage areas, and is configured to, in response to a first write request from the host, write data included in the first write request into first storage areas corresponding to a zone indicated by the first write request.

公开(公告)号：US20220066689A1

公开(公告)日：2022-03-03

申请号：US17238680

申请日：2021-04-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Haesung JUNG ,  Sungho SEO ,  Myungsub SHIN ,  Seongyong JANG

IPC: G06F3/06

Abstract: Provided are a storage device configured to perform high-speed link startup and a storage system including the storage device. The storage system performs data communication through a connected transmission lane and a connected reception lane from among a plurality of lanes between a host and the storage device. The host transmits an activate period of the connected transmission lane, which is less than a first time period, to the connected reception lane, and the storage device receives the activate period of the connected reception lane, which is less than the first time period. The host and the storage device perform link startup in a high-speed mode through the connected transmission lane and the connected reception lane, based on the activate period being less than the first time period.

公开(公告)号：US20210374079A1

公开(公告)日：2021-12-02

申请号：US17321916

申请日：2021-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myungsub SHIN ,  Sungho SEO ,  Kwanwoo NOH ,  Seongyong JANG ,  Haesung JUNG

IPC: G06F13/16 ,  G06F13/18

Abstract: A host controller interface configured to provide interfacing between a host device and a storage device includes processing circuitry; a doorbell register configured to store a head pointer and a tail pointer of one or more first queues; and an entry buffer configured to store a first command from one of the one or more first queues in the entry buffer, wherein the processing circuitry is configured to, determine an order in which the commands of the one or more first queues are to be processed, route the first command to be stored in the entry buffer according to the determined order, and route a first response to be stored in one of one or more second queues.