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1.发明申请公开(公告)号：US20180081556A1
公开(公告)日：2018-03-22
申请号：US15681574
申请日：2017-08-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Youngmin LEE , Ji-Seung YOUN , Sungho SEO , Hyuntae PARK , Hwaseok OH , JinHyeok CHOI
IPC: G06F3/06
CPC classification number: G06F3/0607 , G06F3/061 , G06F3/064 , G06F3/0661 , G06F3/0683 , G06F12/0246 , G06F2212/7201 , G06F2212/7202 , G06F2212/7203 , G06F2212/7207
Abstract: Disclosed is a storage device which includes a nonvolatile memory device and a controller. The controller communicates with a host through a first port, communicates with an external storage device through a second port, and controls the nonvolatile memory device based on first mapping information. The controller is configured to receive second mapping information from the external storage device, receive first write data from the host and to selectively transmit first write data to the external storage device based on the second mapping information.
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公开(公告)号：US20250021129A1
公开(公告)日：2025-01-16
申请号：US18897011
申请日：2024-09-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kwanwoo NOH , Sungho SEO , Yongwoo JEONG , Dongwoo NAM , Myungsub SHIN , Hyunkyu JANG
Abstract: A storage device and a storage system including the same are provided. The storage device includes a reference clock pin configured to receive a reference clock signal from a host, a reference clock frequency determination circuitry configured to determine a reference clock frequency from the reference clock signal received through the reference clock pin, and a device controller circuitry configured to perform a high speed mode link startup between the host and the storage device according to the reference clock frequency.
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3.发明申请公开(公告)号：US20220066689A1
公开(公告)日：2022-03-03
申请号：US17238680
申请日：2021-04-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Haesung JUNG , Sungho SEO , Myungsub SHIN , Seongyong JANG
IPC: G06F3/06
Abstract: Provided are a storage device configured to perform high-speed link startup and a storage system including the storage device. The storage system performs data communication through a connected transmission lane and a connected reception lane from among a plurality of lanes between a host and the storage device. The host transmits an activate period of the connected transmission lane, which is less than a first time period, to the connected reception lane, and the storage device receives the activate period of the connected reception lane, which is less than the first time period. The host and the storage device perform link startup in a high-speed mode through the connected transmission lane and the connected reception lane, based on the activate period being less than the first time period.
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公开(公告)号：US20210374079A1
公开(公告)日：2021-12-02
申请号：US17321916
申请日：2021-05-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Myungsub SHIN , Sungho SEO , Kwanwoo NOH , Seongyong JANG , Haesung JUNG
Abstract: A host controller interface configured to provide interfacing between a host device and a storage device includes processing circuitry; a doorbell register configured to store a head pointer and a tail pointer of one or more first queues; and an entry buffer configured to store a first command from one of the one or more first queues in the entry buffer, wherein the processing circuitry is configured to, determine an order in which the commands of the one or more first queues are to be processed, route the first command to be stored in the entry buffer according to the determined order, and route a first response to be stored in one of one or more second queues.
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公开(公告)号：US20210216223A1
公开(公告)日：2021-07-15
申请号：US17142627
申请日：2021-01-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kwanwoo NOH , Sungho SEO , Yongwoo JEONG
IPC: G06F3/06 , G06F1/04 , G06F9/4401
Abstract: Disclosed is a storage device which includes an interface circuit that exchanges data with a host device, and a power management unit that supplies a power to the interface circuit. The interface circuit includes a first input terminal receiving a first signal from the host device, a second input terminal receiving a second signal complementary to the first signal from the host device, a receive module processing the first signal and the second signal, a squelch circuit detecting levels of the first signal and the second signal, and a reference clock detector detecting whether a reference clock for operating the storage device is received. The power management unit selectively supplies a power to the squelch circuit based on a result of the detection by the reference clock detector.
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Patent Agency Ranking
公开(公告)号：US20240103592A1
公开(公告)日：2024-03-28
申请号：US18347231
申请日：2023-07-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sanghyun LEE , Jungmin OH , Yoseob KWAK , Joohong KIM , Sungho SEO
Abstract: An electronic device is provided. The electronic device includes a temperature sensor, a communication circuit, a memory, and a processor. The processor identifies whether the temperature measured through the temperature sensor satisfies a specified condition, in a state of performing data transmission or reception through a call channel between an external electronic device and the electronic device, adjusts the bit rate of a codec that encodes data to be transmitted through the call channel when the measured temperature satisfies the specified condition, and blocks data transmission and/or reception through a radio bearer mapped to a packet data network (PDN) corresponding to an internet protocol (IP) data type among data to be transmitted by the electronic device.
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公开(公告)号：US20220206966A1
公开(公告)日：2022-06-30
申请号：US17467929
申请日：2021-09-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jeongsu KIM , Kwanwoo NOH , Sungho SEO , Yongwoo JEONG
Abstract: A method of operating a storage device includes receiving a first bit sequence including a request for changing a data rate from a host according to a first data rate through an input signal pin; sending a second bit sequence including a response to the request for changing a data rate to the host at the first data rate through an output signal pin; and changing the data rate to a second data rate according to whether a tail-of-burst (TOB) indicating an end of the second bit sequence is output.
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公开(公告)号：US20180088854A1
公开(公告)日：2018-03-29
申请号：US15697900
申请日：2017-09-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kwanwoo NOH , Hyuntae PARK , Sungho SEO , Hwaseok OH , Youngmin LEE , JinHyeok CHOI
CPC classification number: G06F3/0634 , G06F3/0611 , G06F3/0632 , G06F11/0787 , G06F13/4239 , G06F13/4247 , G11C5/04
Abstract: An electronic device includes an application processor; and a first storage device that is, connected to the application processor and directly communicates with the application processor, and connected to a second storage device such that the second storage device communicates with the application processor through the first storage device, wherein the first storage device includes a reset converter configured to generate a software reset signal in response to a hardware reset signal received from the application processor, and wherein the software reset signal resets the second storage device.
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公开(公告)号：US20210397368A1
公开(公告)日：2021-12-23
申请号：US17328225
申请日：2021-05-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Dongwoo NAM , Sungho SEO , Kwanwoo NOH , Myungsub SHIN , Haesung JUNG
IPC: G06F3/06
Abstract: A link startup method of a storage device connected to a host through a plurality of lanes includes performing an initialization operation in the storage device; establishing data communication through a connected transmission lane and a connected reception lane among the plurality of lanes; transmitting a high speed link up message to the host through the connected transmission lane of the storage device; and performing a link startup operation in a high speed mode through the connected transmission lane of the storage device and the connected reception lane of the host, based on the high speed link up message transmitted by the storage device.
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公开(公告)号：US20210263550A1
公开(公告)日：2021-08-26
申请号：US17179830
申请日：2021-02-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kwanwoo NOH , Sungho SEO , Yongwoo JEONG , Dongwoo NAM , Myungsub SHIN , Hyunkyu JANG
Abstract: A storage device and a storage system including the same are provided. The storage device includes a reference clock pin configured to receive a reference clock signal from a host, a reference clock frequency determination circuitry configured to determine a reference clock frequency from the reference clock signal received through the reference clock pin, and a device controller circuitry configured to perform a high speed mode link startup between the host and the storage device according to the reference clock frequency.
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