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    SEMICONDUCTOR PACKAGE
    1.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20250118652A1

    公开(公告)日：2025-04-10

    申请号：US18738701

    申请日：2024-06-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seunghwan Baek

    IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H01L25/18 ,  H10B80/00

    Abstract: An example semiconductor package comprises a lower semiconductor package and an upper semiconductor package. The lower semiconductor package includes a first substrate and a dielectric pattern on a top surface of the first substrate. The first substrate includes first pads. The dielectric pattern includes stepwise openings that expose the first pads. A cross-section of a stepwise opening has a pair of stepwise structures. A stepwise structure includes a first lateral surface, a second lateral surface, and a first bottom surface that connects the first and second lateral surfaces with each other. The first lateral surface is connected with a top surface of a first pad. The second lateral surface is connected with a top surface of the dielectric pattern. The upper semiconductor package includes connection terminals on a lower portion of the upper semiconductor package. The connection terminals are respectively attached to the first pads.

    Semiconductor package and method of manufacturing the same
    3.
    发明授权
    Semiconductor package and method of manufacturing the same 有权

    公开(公告)号：US11302572B2

    公开(公告)日：2022-04-12

    申请号：US16983298

    申请日：2020-08-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dowan Kim ,  Doohwan Lee ,  Seunghwan Baek

    IPC: H01L21/768 ,  H01L23/538 ,  H01L23/00 ,  H01L23/31

    Abstract: A method of manufacturing a semiconductor package may include forming a first substrate including a redistribution layer, providing a second substrate including a semiconductor chip and an interconnection layer on the first substrate to connect the semiconductor chip to the redistribution layer, forming a first encapsulation layer covering the second substrate, and forming a via structure penetrating the first encapsulation layer. The forming the via structure may include forming a first via hole in the first encapsulation layer, forming a photosensitive material layer in the first via hole, exposing and developing the photosensitive material layer in the first via hole to form a second encapsulation layer having a second via hole, and filling the second via hole with a conductive material. A surface roughness of a sidewall of the first encapsulation layer may be greater than a surface roughness of a sidewall of the second encapsulation layer.

    Semiconductor package and method of manufacturing the same
    4.
    发明授权
    Semiconductor package and method of manufacturing the same 有权

    公开(公告)号：US11721577B2

    公开(公告)日：2023-08-08

    申请号：US17714546

    申请日：2022-04-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dowan Kim ,  Doohwan Lee ,  Seunghwan Baek

    IPC: H01L21/768 ,  H01L23/538 ,  H01L23/00 ,  H01L23/31

    CPC classification number: H01L21/76802 ,  H01L21/76877 ,  H01L23/31 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/94

    Abstract: A method of manufacturing a semiconductor package may include forming a first substrate including a redistribution layer, providing a second substrate including a semiconductor chip and an interconnection layer on the first substrate to connect the semiconductor chip to the redistribution layer, forming a first encapsulation layer covering the second substrate, and forming a via structure penetrating the first encapsulation layer. The forming the via structure may include forming a first via hole in the first encapsulation layer, forming a photosensitive material layer in the first via hole, exposing and developing the photosensitive material layer in the first via hole to form a second encapsulation layer having a second via hole, and filling the second via hole with a conductive material. A surface roughness of a sidewall of the first encapsulation layer may be greater than a surface roughness of a sidewall of the second encapsulation layer.

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