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公开(公告)号：US20240036745A1
公开(公告)日：2024-02-01
申请号：US18156266
申请日：2023-01-18
发明人： Seungki HONG
IPC分类号： G06F3/06
CPC分类号： G06F3/0625 , G06F3/0629 , G06F3/0673
摘要： Disclosed is a memory device, which may include memory banks including a plurality of memory cells, row address repeaters that transfer a row address to the memory banks, and control logic that controls data input/output of the memory banks. The memory banks may be grouped into a plurality of bank groups, and the row address repeaters may be grouped into a plurality of repeater groups respectively corresponding to the plurality of bank groups. The control logic may control the row address repeaters according to activation status of the plurality of bank groups.
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公开(公告)号：US20240112716A1
公开(公告)日：2024-04-04
申请号：US18119458
申请日：2023-03-09
发明人： Seungki HONG , Seung-jun LEE , Minho CHOI
IPC分类号： G11C11/406 , G11C11/408
CPC分类号： G11C11/406 , G11C11/4085 , G11C11/4087
摘要： A memory device includes plural banks that perform a per-bank refresh (PBR) operation, and an address register that provides a single row address signal to two banks of the plural banks, the two banks simultaneously performing the PBR operation and the single row address signal being shared by the two banks. The two banks activate a word line of each memory cell array based on a single decoded row address signal that is generated based on the single row address signal.
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公开(公告)号：US20240257896A1
公开(公告)日：2024-08-01
申请号：US18543687
申请日：2023-12-18
发明人： Seungki HONG , Seungjun LEE
CPC分类号： G11C29/44 , G11C29/18 , G11C2029/1802
摘要： A repair circuit, including a first fail address latch configured to latch a first fail address and a second fail address corresponding to a first bank; a second fail address latch configured to latch a third fail address and a fourth fail address corresponding to a second bank different from the first bank; a fail address multiplexer configured merge the first fail address and the third fail address into a first merge address, and to merge the second fail address and the fourth fail address into a second merge address; a comparison circuit configured to compare the first and second merge addresses with merged decoded row addresses to generate first and second hit signals; a logic operator configured to output a valid hit pre-signal based on the first and second hit signals; and a valid hit latch configured output a valid hit signal based on the valid hit pre-signal.
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公开(公告)号：US20230298655A1
公开(公告)日：2023-09-21
申请号：US17882242
申请日：2022-08-05
发明人： Seungki HONG
IPC分类号： G11C11/406 , G11C29/00
CPC分类号： G11C11/40622 , G11C11/40615 , G11C29/783
摘要： A memory device is provided. The memory device includes: a memory cell array including a plurality of rows; and a refresh control circuit including a plurality of registers each configured to store a row address. The refresh control circuit is configured to: determine, based on an incoming row address satisfying a replacement condition, in a first determination, whether to replace a first row address stored in a first register among the plurality of registers with the incoming row address based on a replacement probability; maintain the first row address stored in the first register or replace the first row address stored in the first register with the incoming row address based on a first result of the first determination; and determine, in a second determination, a victim row address to be refreshed based on a second row address stored in a second register among the plurality of registers.
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公开(公告)号：US20240160732A1
公开(公告)日：2024-05-16
申请号：US18504430
申请日：2023-11-08
发明人： Youngjae PARK , Seungki HONG , Hyunbo KIM , Insu CHOI
IPC分类号： G06F21/55
CPC分类号： G06F21/554 , G06F2221/034
摘要： Provided is a memory device including a memory cell array including a plurality of memory cell rows, the plurality of memory cell rows being grouped into a plurality of segments, a row decoder connected to the plurality of memory cell rows, and a refresh control circuit configured to generate a refresh control signal for controlling a refresh operation on the plurality of memory cell rows.
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公开(公告)号：US20220208251A1
公开(公告)日：2022-06-30
申请号：US17346633
申请日：2021-06-14
发明人： Seungki HONG , Wonil BAE , Heonsu JEONG
IPC分类号： G11C11/4091 , G11C11/408 , G11C11/4094 , G11C11/406 , G11C7/10
摘要： A semiconductor memory device and a memory system are provided. The semiconductor memory device includes a fingerprint read signal generator configured to generate a fingerprint read signal in response to a refresh counting control signal, a memory cell array comprising a plurality of sub memory cell array blocks, a fingerprint output unit configured to receive data output from memory cells connected to one selected among a plurality of word lines and one selected among a plurality of bit lines of one among the plurality of sub memory cell array blocks in response to the fingerprint read signal to generate fingerprint data, and a pseudorandom number generator configured to perform a linear feedback shifting operation in response to an active command to generate sequence data, receive the fingerprint data in response to the fingerprint read signal, and generate the sequence data based on the fingerprint data.
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公开(公告)号：US20220199148A1
公开(公告)日：2022-06-23
申请号：US17354364
申请日：2021-06-22
发明人： Seungki HONG , Geuntae Park
IPC分类号： G11C11/406 , G11C11/408 , G11C11/4094 , G11C11/4091
摘要： A semiconductor memory device and a memory system are provided. The semiconductor memory device includes a memory cell array, a normal refresh row address generator, a hammer refresh row address generator, a refresh selection signal generator, and a selector. The normal and hammer refresh row address generators generates a normal refresh row address and a hammer refresh row address, respectively, in response to a refresh counting control signal. The refresh selection signal generator sequentially generates normal and hammer refresh selection signals in response to the refresh counting control signal. The selector selects the normal refresh row address or the hammer refresh row address in response to the normal and hammer refresh selection signals. A normal refresh operation and a hammer refresh operation are sequentially performed on a memory cell array block among plural memory cell array blocks in response to the refresh row address.
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公开(公告)号：US20240185906A1
公开(公告)日：2024-06-06
申请号：US18413924
申请日：2024-01-16
发明人： Jongmin BANG , Seungki HONG
IPC分类号： G11C11/406 , G11C11/408 , G11C11/4091
CPC分类号： G11C11/40615 , G11C11/40622 , G11C11/4085 , G11C11/4087 , G11C11/4091
摘要： A semiconductor memory device includes a command and address generator configured to decode a command to generate an active command, and generate an address applied with the active command as a row address, a control signal generator configured to generate sequence data changing with a random sequence in response to the active command, and generate a random pick signal when the sequence data is equal to previously stored comparison data, and a memory cell array comprising an odd page memory cell array including a plurality of first memory cells and an even page memory cell array including a plurality of second memory cells, and configured to simultaneously perform the active operation and a hidden hammer refresh operation on the selected first and second memory cells in response to the row address when the random pick signal is activated in response to the active command.
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公开(公告)号：US20230170009A1
公开(公告)日：2023-06-01
申请号：US17722652
申请日：2022-04-18
发明人： Jongmin BANG , Seungki HONG
IPC分类号： G11C11/406 , G11C11/408 , G11C11/4091
CPC分类号： G11C11/40615 , G11C11/4085 , G11C11/4087 , G11C11/4091 , G11C11/40622
摘要： A semiconductor memory device includes a command and address generator configured to decode a command to generate an active command, and generate an address applied with the active command as a row address, a control signal generator configured to generate sequence data changing with a random sequence in response to the active command, and generate a random pick signal when the sequence data is equal to previously stored comparison data, and a memory cell array comprising an odd page memory cell array including a plurality of first memory cells and an even page memory cell array including a plurality of second memory cells, and configured to simultaneously perform the active operation and a hidden hammer refresh operation on the selected first and second memory cells in response to the row address when the random pick signal is activated in response to the active command.
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公开(公告)号：US20230143468A1
公开(公告)日：2023-05-11
申请号：US17834320
申请日：2022-06-07
发明人： Seungki HONG
IPC分类号： G11C11/406
CPC分类号： G11C11/40615 , G11C11/40622 , G11C11/40603
摘要： An operating method of a memory device, the method including, receiving a row address, determining whether an operating mode is a byte mode, counting up an access count value for the row address while ignoring a page bit, when the operating mode is the byte mode, selecting a target row hammer address among target row addresses using access count values for the target row hammer address, calculating a victim row address corresponding to the target row hammer address, and performing a target refresh operation on the victim row address.
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