公开(公告)号：US20230057061A1

公开(公告)日：2023-02-23

申请号：US17722630

申请日：2022-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seyeong SEOK ,  Dongwoo KIM ,  Hosin SONG ,  Jonghyeon CHANG

IPC: H01L23/00 ,  H01L25/10 ,  H01L25/065 ,  H01L23/538

Abstract: A semiconductor chip that includes a chip body that has a first side surface, a second side surface, a third side surface, and a fourth side surface; a central region at a central portion of the chip body; and a peripheral region at a peripheral portion of the chip body and adjacent to at least one of the first side surface to the fourth side surface, wherein the peripheral region includes a first unit region that includes a plurality of first bumps of a first bump density, and a second unit region that includes a plurality of second bumps of a second bump density higher than the first bump density.

公开(公告)号：US20250120009A1

公开(公告)日：2025-04-10

申请号：US18825308

申请日：2024-09-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongwoo KIM ,  Seyeong SEOK ,  Daseul LEE ,  Jonghyeon CHANG

IPC: H05K1/02 ,  H01L23/00 ,  H05K1/11 ,  H05K1/18

Abstract: A semiconductor package includes a base substrate including a lower surface; a semiconductor chip on the base substrate; and a plurality of connection bumps on the lower surface of the base substrate, wherein the plurality of connection bumps includes a first group including connection bumps arranged on the lower surface in a first direction, and a second group including connection bumps arranged on the lower surface in a second direction, the second direction having a first angle with respect to the first direction, the connection bumps of the first group are offset from each other in the first direction, and the connection bumps of the second group are offset from each other in the second direction.

公开(公告)号：US20240404972A1

公开(公告)日：2024-12-05

申请号：US18799579

申请日：2024-08-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seyeong SEOK ,  Un-Byoung Kang ,  Chungsun Lee

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18

Abstract: A semiconductor package may include: a first redistribution substrate; a first die above the first redistribution substrate; a second redistribution substrate on the first die; a first bump formed on the first die, and connecting the first die to the second redistribution substrate; a first molding portion enclosing the first die and surrounding the first bump; and an outer terminal on a bottom surface of the first redistribution substrate, wherein the second redistribution substrate comprises an insulating pattern and a conductive pattern in the insulating pattern to be in contact with the first bump, and wherein, at an interface of the second redistribution substrate and the first bump, the conductive pattern of the second redistribution substrate and the first bump are formed of the same material to form a single body or structure.