公开(公告)号：US12046546B2

公开(公告)日：2024-07-23

申请号：US17568345

申请日：2022-01-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shlege Lee ,  Dongok Kwak ,  Sunwoo Han

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/18

CPC classification number: H01L23/49838 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/16 ,  H01L25/18 ,  H01L2224/16227

Abstract: A package substrate includes; a conductive line extending in a first horizontal direction, a conductive pad on an upper surface of the package substrate and horizontally spaced apart from the conductive line in a second horizontal direction, and a protective layer covering the conductive line and including an opening selectively exposing a portion of the conductive pad. The opening has an elongated elliptical shape having a minor axis defined by a width extending in the first horizontal direction and a major axis defined by a length extending in the second horizontal direction.

公开(公告)号：US20240429146A1

公开(公告)日：2024-12-26

申请号：US18639148

申请日：2024-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minwoo Cho ,  Hyunggil Baek ,  Shlege Lee

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor package includes a lower substrate that includes a chip mounting region and a peripheral region, where the lower substrate includes lower redistribution wirings; a first semiconductor chip on the chip mounting region, where the first semiconductor chip includes: a silicon substrate that includes a first surface and a second surface that are opposite to each other, an activation layer on the second surface, and a chip redistribution wiring layer that is on the first surface and includes a plurality of chip redistribution wirings that are electrically insulated from the activation layer; a plurality of connecting members that are on the peripheral region and are electrically connected to the lower redistribution wirings; and an upper substrate on the plurality of connecting members, and where at least a portion of the first semiconductor chip is in a through cavity defined by the upper substrate.