公开(公告)号：US11688656B2

公开(公告)日：2023-06-27

申请号：US17098748

申请日：2020-11-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyoung Oh ,  Hyunggil Baek ,  Seunghwan Kim ,  Jungjoo Kim ,  Jongho Park ,  Yongkwan Lee

IPC: H01L23/16 ,  H01L25/065 ,  H01L23/498 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/16 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5389 ,  H01L25/0657

Abstract: A semiconductor package is provided. The semiconductor package includes: a first package substrate; a first semiconductor chip on the first package substrate; an interposer substrate including a lower surface facing the first package substrate, an upper surface opposite to the lower surface, and an upper conductive pad in the upper surface of the interposer substrate; a first dam structure on the upper surface of the interposer substrate and extending along an edge of the upper conductive pad; a first molding layer in contact with the lower and upper surfaces of the interposer substrate and with an outer wall of the first dam structure; and a conductive connector in contact with an inner wall of the at least one first dam structure and with the upper conductive pad.

公开(公告)号：US20220367416A1

公开(公告)日：2022-11-17

申请号：US17671065

申请日：2022-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongkwan Lee ,  Seunghwan Kim ,  Jungjoo Kim ,  Jongwan Kim ,  Hyunki Kim ,  Junwoo Park ,  Hyunggil Baek ,  Junga Lee ,  Taejun Jeon

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538

Abstract: A semiconductor package includes a package substrate having a communication hole extending from an upper surface of the package substrate to a lower surface of the package substrate, a semiconductor chip attached to the upper surface of the package substrate, an auxiliary chip attached to the lower surface of the package substrate, external connection terminals attached to the lower surface of the package substrate and spaced apart from the auxiliary chip, and an encapsulant encapsulating the semiconductor chip and the auxiliary chip and filling the communication hole.

公开(公告)号：US12087650B2

公开(公告)日：2024-09-10

申请号：US18315558

申请日：2023-05-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyoung Oh ,  Hyunggil Baek ,  Seunghwan Kim ,  Jungjoo Kim ,  Jongho Park ,  Yongkwan Lee

IPC: H01L23/16 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/16 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5389 ,  H01L25/0657

Abstract: A semiconductor package is provided. The semiconductor package includes: a first package substrate; a first semiconductor chip on the first package substrate; an interposer substrate including a lower surface facing the first package substrate, an upper surface opposite to the lower surface, and an upper conductive pad in the upper surface of the interposer substrate; a first dam structure on the upper surface of the interposer substrate and extending along an edge of the upper conductive pad; a first molding layer in contact with the lower and upper surfaces of the interposer substrate and with an outer wall of the first dam structure; and a conductive connector in contact with an inner wall of the at least one first dam structure and with the upper conductive pad.

公开(公告)号：US20230180381A1

公开(公告)日：2023-06-08

申请号：US18071903

申请日：2022-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kanggyune Lee ,  Hyunggil Baek ,  Youngja Kim ,  Seungjin Lee

IPC: H05K1/02 ,  H01L23/544 ,  H01L23/498 ,  H01L25/10

CPC classification number: H05K1/0269 ,  H01L23/544 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L25/105 ,  H01L2223/54426 ,  H05K1/113

Abstract: A printed circuit board includes a substrate base; a plurality of ball lands arranged on a surface of the substrate base; a cutting position identification mark disposed on a corner of the surface of the substrate base; and at least one alignment mark disposed on the surface of the substrate base to be spaced apart from the ball lands and exposed to the outside, wherein top surfaces of the ball lands and a top surface of the at least one alignment mark are at substantially the same vertical level and the ball lands and the at least one alignment mark include the same material.

公开(公告)号：US10418335B2

公开(公告)日：2019-09-17

申请号：US15850336

申请日：2017-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yun-Rae Cho ,  Sundae Kim ,  Hyunggil Baek ,  Namgyu Baek ,  Seunghun Shin ,  Donghoon Won

IPC: H01L23/00 ,  H01L21/02 ,  H01L21/78 ,  H01L23/58

Abstract: A method of dividing a substrate includes preparing a substrate including a crystalline semiconductor layer having a scribe lane region and device regions, a dielectric layer on the crystalline semiconductor layer, and a partition structure in physical contact with the dielectric layer and provided on the scribe lane region of the crystalline semiconductor layer, forming an amorphous region in the crystalline semiconductor layer, and performing a grinding process on the crystalline semiconductor layer after the forming of the amorphous region. The amorphous region is formed in the scribe lane region of the crystalline semiconductor layer.

公开(公告)号：US12208541B2

公开(公告)日：2025-01-28

申请号：US17746454

申请日：2022-05-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngja Kim ,  Hyunggil Baek ,  Younhwan Shin

IPC: B28D5/02 ,  C01B32/25

Abstract: A dicing blade includes: a first blade portion and a second blade portion at least partially surrounding the first blade portion, wherein the first blade portion includes: a first bonding layer; first diamond particles disposed in the first bonding layer and having a first density in the first bonding layer; and first metal particles disposed in the first bonding layer, and wherein the second blade portion includes: a second bonding layer at least partially surrounding the first bonding layer; and second diamond particles disposed in the second bonding layer and having a second density in the second bonding layer, wherein the second density is higher than the first density.

公开(公告)号：US12205925B2

公开(公告)日：2025-01-21

申请号：US17671065

申请日：2022-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongkwan Lee ,  Seunghwan Kim ,  Jungjoo Kim ,  Jongwan Kim ,  Hyunki Kim ,  Junwoo Park ,  Hyunggil Baek ,  Junga Lee ,  Taejun Jeon

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538

Abstract: A semiconductor package includes a package substrate having a communication hole extending from an upper surface of the package substrate to a lower surface of the package substrate, a semiconductor chip attached to the upper surface of the package substrate, an auxiliary chip attached to the lower surface of the package substrate, external connection terminals attached to the lower surface of the package substrate and spaced apart from the auxiliary chip, and an encapsulant encapsulating the semiconductor chip and the auxiliary chip and filling the communication hole.

公开(公告)号：US20230260926A1

公开(公告)日：2023-08-17

申请号：US18107143

申请日：2023-02-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongkwan Lee ,  Seunghwan Kim ,  Jungjoo Kim ,  Jongwan Kim ,  Junwoo Park ,  Hyunggil Baek ,  Junga Lee

IPC: H01L23/544 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L25/10 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/544 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/562 ,  H01L25/105 ,  H01L23/5383 ,  H01L23/5385 ,  H01L21/4846 ,  H01L21/563 ,  H01L2224/16227 ,  H01L24/16 ,  H01L2224/32225 ,  H01L24/32 ,  H01L2224/73204 ,  H01L24/73 ,  H01L2223/54426 ,  H01L2224/92125 ,  H01L24/92

Abstract: A semiconductor package includes an interposer including an upper pad and an upper passivation layer partially covering the upper pad, a semiconductor chip disposed on the interposer, a conductor pattern disposed on the interposer, a guide pattern disposed on the interposer while including a main opening and at least one sub-opening connected to the main opening, a support disposed on the interposer while including a core portion and a peripheral portion surrounding the core portion, a lower surface of the support being disposed in the main opening of the guide pattern, an upper redistribution structure disposed on the semiconductor chip and connected to the conductor pattern and the guide pattern, and an encapsulant between the interposer and the upper redistribution structure. The encapsulant contacts an inner wall of the main opening, an inner wall of the at least one sub-opening and a side surface of the support.

公开(公告)号：US10916509B2

公开(公告)日：2021-02-09

申请号：US16530993

申请日：2019-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yun-Rae Cho ,  Sundae Kim ,  Hyunggil Baek ,  Namgyu Baek ,  Seunghun Shin ,  Donghoon Won

IPC: H01L21/78 ,  H01L23/00 ,  H01L21/02 ,  H01L23/58

Abstract: A method of dividing a substrate includes preparing a substrate including a crystalline semiconductor layer having a scribe lane region and device regions, a dielectric layer on the crystalline semiconductor layer, and a partition structure in physical contact with the dielectric layer and provided on the scribe lane region of the crystalline semiconductor layer, forming an amorphous region in the crystalline semiconductor layer, and performing a grinding process on the crystalline semiconductor layer after the forming of the amorphous region. The amorphous region is formed in the scribe lane region of the crystalline semiconductor layer.

公开(公告)号：US20240429146A1

公开(公告)日：2024-12-26

申请号：US18639148

申请日：2024-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minwoo Cho ,  Hyunggil Baek ,  Shlege Lee

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor package includes a lower substrate that includes a chip mounting region and a peripheral region, where the lower substrate includes lower redistribution wirings; a first semiconductor chip on the chip mounting region, where the first semiconductor chip includes: a silicon substrate that includes a first surface and a second surface that are opposite to each other, an activation layer on the second surface, and a chip redistribution wiring layer that is on the first surface and includes a plurality of chip redistribution wirings that are electrically insulated from the activation layer; a plurality of connecting members that are on the peripheral region and are electrically connected to the lower redistribution wirings; and an upper substrate on the plurality of connecting members, and where at least a portion of the first semiconductor chip is in a through cavity defined by the upper substrate.