公开(公告)号：US12046538B2

公开(公告)日：2024-07-23

申请号：US18354068

申请日：2023-07-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sonkwan Hwang ,  Taeseong Kim ,  Hoonjoo Na ,  Kwangjin Moon ,  Hyungjun Jeon

IPC: H01L21/00 ,  H01L21/768 ,  H01L23/48 ,  H01L23/528 ,  H01L25/065 ,  H01L27/088 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/528 ,  H01L25/0657 ,  H01L27/0886 ,  H01L24/02 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2225/06513 ,  H01L2225/06544

Abstract: A semiconductor device including a semiconductor substrate, an integrated circuit layer on the semiconductor substrate, first to nth metal wiring layers (where n is a positive integer) sequentially stacked on the semiconductor substrate and the integrated circuit layer, a first through via structure extending in a vertical direction toward the semiconductor substrate from a first via connection metal wiring layer, which is one of the second to nth metal wiring layers other than the first metal wiring layer, and passing through the semiconductor substrate, and a second through via structure being apart from the first through via structure, extending in a vertical direction toward the semiconductor substrate from a second via connection metal wiring layer, which is one of the second to nth metal wiring layers other than the first metal wiring layer, and passing through the semiconductor substrate may be provided.

公开(公告)号：US12166000B2

公开(公告)日：2024-12-10

申请号：US17541719

申请日：2021-12-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoonjoo Na ,  Jungseob So ,  Taeseong Kim ,  Sohye Cho ,  Sonkwan Hwang

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/18

Abstract: The semiconductor device includes a lower chip structure including a peripheral circuit, a first memory chip structure on the lower chip structure, and a second memory chip structure on the first memory chip structure. The first memory chip structure includes a first stack structure and a first vertical memory structure. The first stack structure includes first gate lines stacked in a vertical direction and extending in a first horizontal direction. The first vertical memory structure penetrates through the first gate lines in the vertical direction. The second memory chip structure includes a second stack structure and a second vertical memory structure. The second stack structure includes second gate lines stacked in the vertical direction and extending in a second horizontal direction, perpendicular to the first horizontal direction. The second vertical memory structure penetrates through the second gate lines in the vertical direction.

公开(公告)号：US11749586B2

公开(公告)日：2023-09-05

申请号：US17514218

申请日：2021-10-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sonkwan Hwang ,  Taeseong Kim ,  Hoonjoo Na ,  Kwangjin Moon ,  Hyungjun Jeon

IPC: H01L21/00 ,  H01L23/48 ,  H01L27/088 ,  H01L25/065 ,  H01L21/768 ,  H01L23/528 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/528 ,  H01L25/0657 ,  H01L27/0886 ,  H01L24/02 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05569 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2225/06513 ,  H01L2225/06544

Abstract: A semiconductor device including a semiconductor substrate, an integrated circuit layer on the semiconductor substrate, first to nth metal wiring layers (where n is a positive integer) sequentially stacked on the semiconductor substrate and the integrated circuit layer, a first through via structure extending in a vertical direction toward the semiconductor substrate from a first via connection metal wiring layer, which is one of the second to nth metal wiring layers other than the first metal wiring layer, and passing through the semiconductor substrate, and a second through via structure being apart from the first through via structure, extending in a vertical direction toward the semiconductor substrate from a second via connection metal wiring layer, which is one of the second to nth metal wiring layers other than the first metal wiring layer, and passing through the semiconductor substrate may be provided.