公开(公告)号：US09747058B2

公开(公告)日：2017-08-29

申请号：US14730632

申请日：2015-06-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gi-Won Oh ,  Ju-Yun Jung ,  Soo-Hyeong Kim ,  Hyun-Joong Kim

IPC: G11C29/00 ,  G06F3/06 ,  G11C5/02 ,  G11C7/10 ,  G11C8/00 ,  G11C5/04

CPC classification number: G06F3/0688 ,  G06F3/0619 ,  G06F3/0635 ,  G06F3/0659 ,  G11C5/02 ,  G11C5/04 ,  G11C7/1012 ,  G11C8/00 ,  G11C29/76 ,  G11C2207/108

Abstract: A semiconductor memory device includes a memory cell array including a plurality of cell cores which include a first cell core corresponding to a first channel that is a normal channel and a second cell core corresponding to a second channel that is a failed channel; and an access circuit configured to perform address remapping by converting a first address of at least a first failed cell in the first cell core into a second address of at least a second cell in the second cell core, and to transmit data of at least the second cell through the first channel.

公开(公告)号：US11966622B2

公开(公告)日：2024-04-23

申请号：US17690163

申请日：2022-03-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Oh Huh ,  Jong Kyu Choi ,  Soo-Hyeong Kim ,  Dong Hee Kim ,  Young San Kang

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: A memory storage device that performs real-time monitoring is provided. The memory storage device comprises a memory controller, and a status indicating module/circuit, wherein the memory controller is configured to perform a first a second initialization operation, the first and second initialization operations performed in response to turning-on of the memory storage device, to generate a first status parameter regarding a status of the memory storage device in which the first initialization operation is performed, and to generate a second status parameter regarding the status of the memory storage device in which a second initialization operation is performed. The status indicating circuit includes a first transistor configured to operate on the basis of the first status parameter, a first resistor connected to the first transistor, a second transistor configured to operate on the basis of the second status parameter, and a second resistor connected to the second transistor.