Memory storage device, an operation method of the memory storage device, test method and electronic device

    公开(公告)号:US11966622B2

    公开(公告)日:2024-04-23

    申请号:US17690163

    申请日:2022-03-09

    CPC classification number: G06F3/0655 G06F3/0604 G06F3/0679

    Abstract: A memory storage device that performs real-time monitoring is provided. The memory storage device comprises a memory controller, and a status indicating module/circuit, wherein the memory controller is configured to perform a first a second initialization operation, the first and second initialization operations performed in response to turning-on of the memory storage device, to generate a first status parameter regarding a status of the memory storage device in which the first initialization operation is performed, and to generate a second status parameter regarding the status of the memory storage device in which a second initialization operation is performed. The status indicating circuit includes a first transistor configured to operate on the basis of the first status parameter, a first resistor connected to the first transistor, a second transistor configured to operate on the basis of the second status parameter, and a second resistor connected to the second transistor.

    Semiconductor chip and vehicle comprising the same

    公开(公告)号:US11837320B2

    公开(公告)日:2023-12-05

    申请号:US17580702

    申请日:2022-01-21

    CPC classification number: G11C7/1093 G11C7/1066 G11C7/20 G11C8/18 H03K5/135

    Abstract: A semiconductor chip capable of improving signal quality includes a host device, a first memory device which is spaced part from the host device and connected to the host device, a repeater module which is connected to the host device and the first memory device, and a second memory device which is spaced apart from the host device and connected to the repeater module. The first memory device receives a data signal from the host device and generates a recovery clock signal, using the data signal. The repeater module receives the recovery clock signal from the first memory device, receives a first input signal from the host device, and samples the first input signal on the basis of the recovery clock signal to generate a sampling signal. The second memory device receives the sampling signal.

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