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    Memory storage device, an operation method of the memory storage device, test method and electronic device
    4.
    发明授权
    Memory storage device, an operation method of the memory storage device, test method and electronic device 有权

    公开(公告)号：US11966622B2

    公开(公告)日：2024-04-23

    申请号：US17690163

    申请日：2022-03-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sung Oh Huh ,  Jong Kyu Choi ,  Soo-Hyeong Kim ,  Dong Hee Kim ,  Young San Kang

    IPC: G06F3/06

    CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

    Abstract: A memory storage device that performs real-time monitoring is provided. The memory storage device comprises a memory controller, and a status indicating module/circuit, wherein the memory controller is configured to perform a first a second initialization operation, the first and second initialization operations performed in response to turning-on of the memory storage device, to generate a first status parameter regarding a status of the memory storage device in which the first initialization operation is performed, and to generate a second status parameter regarding the status of the memory storage device in which a second initialization operation is performed. The status indicating circuit includes a first transistor configured to operate on the basis of the first status parameter, a first resistor connected to the first transistor, a second transistor configured to operate on the basis of the second status parameter, and a second resistor connected to the second transistor.

    Signal receiving device including sampler, voting circuit, and eye open monitor circuit
    5.
    发明授权
    Signal receiving device including sampler, voting circuit, and eye open monitor circuit 有权

    公开(公告)号：US11870570B2

    公开(公告)日：2024-01-09

    申请号：US17581876

    申请日：2022-01-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Young San Kang ,  Byoung Sul Kim ,  Soo-Hyung Kim ,  Jun-Ho Jo

    IPC: H04L1/00 ,  G11C7/22 ,  H04L1/16 ,  G11C7/14 ,  H04L1/1607

    CPC classification number: H04L1/0042 ,  G11C7/14 ,  G11C7/22 ,  H04L1/0045 ,  H04L1/1678

    Abstract: A signal receiving device includes a sampling device configured to sample an input signal to output a plurality of sampling values, and an output circuit configured to output data based on the sampling values. The output circuit outputs the data by performing majority voting based on first to third sampling values of the sampling values in response to a first control signal, and outputs the data and first and second error count signals based on the first sampling value and fourth and fifth sampling values of the sampling values in response to a second control signal. The first error count signal is generated by comparing the first sampling value sampled under a reference condition with the fourth sampling value sampled under a first offset condition, and the second error count signal is generated by comparing the first sampling value with the fifth sampling value sampled under a second offset condition.

    Semiconductor chip and vehicle comprising the same
    6.
    发明授权
    Semiconductor chip and vehicle comprising the same 有权

    公开(公告)号：US11837320B2

    公开(公告)日：2023-12-05

    申请号：US17580702

    申请日：2022-01-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Young San Kang ,  Dong Hee Kim ,  Jong Kyu Choi ,  Sung Oh Huh

    IPC: G11C7/10 ,  H03K5/135 ,  G11C8/18 ,  G11C7/20

    CPC classification number: G11C7/1093 ,  G11C7/1066 ,  G11C7/20 ,  G11C8/18 ,  H03K5/135

    Abstract: A semiconductor chip capable of improving signal quality includes a host device, a first memory device which is spaced part from the host device and connected to the host device, a repeater module which is connected to the host device and the first memory device, and a second memory device which is spaced apart from the host device and connected to the repeater module. The first memory device receives a data signal from the host device and generates a recovery clock signal, using the data signal. The repeater module receives the recovery clock signal from the first memory device, receives a first input signal from the host device, and samples the first input signal on the basis of the recovery clock signal to generate a sampling signal. The second memory device receives the sampling signal.

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