公开(公告)号：US10083939B2

公开(公告)日：2018-09-25

申请号：US15421386

申请日：2017-01-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-kyoung Seo ,  Cha-jea Jo ,  Soo-hyun Ha

IPC: H01L29/40 ,  H01L25/065 ,  H01L23/532 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L23/3185 ,  H01L23/53238 ,  H01L2224/16145 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06582

Abstract: A semiconductor package includes: a first semiconductor chip in which a through-electrode is provided; a second semiconductor chip connected to a top surface of the first semiconductor chip; a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer; and a second connection bump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.

公开(公告)号：US10991677B2

公开(公告)日：2021-04-27

申请号：US16847987

申请日：2020-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-kyoung Seo ,  Cha-jea Jo ,  Soo-hyun Ha

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/532

Abstract: A semiconductor package includes: a first semiconductor chip in which a through-electrode is provided; a second semiconductor chip connected to a top surface of the first semiconductor chip; a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer, and a second connection hump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.

公开(公告)号：US10373935B2

公开(公告)日：2019-08-06

申请号：US16114795

申请日：2018-08-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-kyoung Seo ,  Cha-jea Jo ,  Soo-hyun Ha

IPC: H01L23/31 ,  H01L23/532 ,  H01L25/065

Abstract: A semiconductor package includes: a first semiconductor chip in which a through-electrode is provided; a second semiconductor chip connected to a top surface of the first semiconductor chip; a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer; and a second connection bump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.

公开(公告)号：US11610865B2

公开(公告)日：2023-03-21

申请号：US17213715

申请日：2021-03-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-kyoung Seo ,  Cha-jea Jo ,  Soo-hyun Ha

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/532

Abstract: A semiconductor package includes a first semiconductor chip in which a through-electrode is provided, a second semiconductor chip connected to a top surface of the first semiconductor chip, a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer, and a second connection bump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.

公开(公告)号：US10658341B2

公开(公告)日：2020-05-19

申请号：US16448703

申请日：2019-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-kyoung Seo ,  Cha-jea Jo ,  Soo-hyun Ha

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/532

Abstract: A semiconductor package includes: a first semiconductor chip in which a through-electrode is provided; a second semiconductor chip connected to a top surface of the first semiconductor chip; a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer, and a second connection hump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.