公开(公告)号：US10026724B2

公开(公告)日：2018-07-17

申请号：US15444277

申请日：2017-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-hwang Kim ,  Jong-bo Shim ,  Sang-uk Han ,  Cha-jea Jo ,  Gun-ho Chang

IPC: H01L25/00 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

Abstract: A method of manufacturing a semiconductor package includes forming at least two partial package chip stacks, each partial package chip stack including at least two semiconductor chips each including a plurality of through substrate vias (TSVs), and including a first mold layer surrounding side surfaces of the at least two semiconductor chips, and sequentially mounting the at least two partial package chip stacks on a package substrate in a direction vertical to a top surface of the package substrate, such that the at least two partial package chip stacks include a first partial package chip stack and a second partial package chip stack directly connected to the first partial package chip stack.

公开(公告)号：US20180006006A1

公开(公告)日：2018-01-04

申请号：US15444277

申请日：2017-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-hwang Kim ,  Jong-bo Shim ,  Sang-uk Han ,  Cha-jea Jo ,  Gun-ho Chang

IPC: H01L25/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L23/3185 ,  H01L24/05 ,  H01L24/16 ,  H01L24/17 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/06596 ,  H01L2225/1023 ,  H01L2225/1058

Abstract: A method of manufacturing a semiconductor package includes forming at least two partial package chip stacks, each partial package chip stack including at least two semiconductor chips each including a plurality of through substrate vias (TSVs), and including a first mold layer surrounding side surfaces of the at least two semiconductor chips, and sequentially mounting the at least two partial package chip stacks on a package substrate in a direction vertical to a top surface of the package substrate, such that the at least two partial package chip stacks include a first partial package chip stack and a second partial package chip stack directly connected to the first partial package chip stack.

公开(公告)号：US09589945B2

公开(公告)日：2017-03-07

申请号：US14804880

申请日：2015-07-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Cha-jea Jo ,  Yun-hyeok Im ,  Tae-je Cho

IPC: H01L25/18 ,  H01L23/367 ,  H01L23/48 ,  H01L25/065 ,  H01L23/36 ,  H01L23/427 ,  H01L23/532 ,  H01L23/31

CPC classification number: H01L25/18 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/427 ,  H01L23/481 ,  H01L23/53223 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L25/0652 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/16195

Abstract: A semiconductor package includes a package base substrate, at least one first semiconductor chip disposed on the package base substrate, and at least one stacked semiconductor chip structure disposed on the package base substrate adjacent to the at least one first semiconductor chip. The at least one stacked semiconductor chip includes a plurality of second semiconductor chips. A penetrating electrode region including a plurality of penetrating electrodes is disposed adjacent to an edge of the at least one stacked semiconductor chip structure.

Abstract translation: 半导体封装包括封装基底基板，设置在封装基底基板上的至少一个第一半导体芯片以及设置在与该至少一个第一半导体芯片相邻的封装基底基板上的至少一个层叠半导体芯片结构。 所述至少一个层叠半导体芯片包括多个第二半导体芯片。 包括多个穿透电极的穿透电极区域设置成与所述至少一个堆叠的半导体芯片结构的边缘相邻。

公开(公告)号：US12113087B2

公开(公告)日：2024-10-08

申请号：US18127110

申请日：2023-03-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji-hwang Kim ,  Jong-bo Shim ,  Sang-uk Han ,  Cha-jea Jo ,  Won-il Lee

IPC: H01L27/146

CPC classification number: H01L27/14634 ,  H01L27/1462 ,  H01L27/14636 ,  H01L27/14638

Abstract: An image sensor package includes an image sensor chip on a package substrate, a logic chip on the package substrate and perpendicularly overlapping the image sensor chip, and a memory chip on the package substrate and perpendicularly overlapping the image sensor chip and logic chip. The logic chip processes a pixel signal output from the image sensor chip. The memory chip is electrically connected to the image sensor chip through a conductive wire and stores at least one of the pixel signal from the image sensor chip or a pixel signal processed by the logic chip. The memory chip receives the pixel signal output from the image sensor chip through the conductive wire and receives the pixel signal processed by the logic chip through the image sensor chip and the conductive wire.

公开(公告)号：US10971535B2

公开(公告)日：2021-04-06

申请号：US15636801

申请日：2017-06-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji-hwang Kim ,  Jong-bo Shim ,  Sang-uk Han ,  Cha-jea Jo ,  Won-il Lee

IPC: H01L27/00 ,  H01L27/146

Abstract: An image sensor package includes an image sensor chip on a package substrate, a logic chip on the package substrate and perpendicularly overlapping the image sensor chip, and a memory chip on the package substrate and perpendicularly overlapping the image sensor chip and logic chip. The logic chip processes a pixel signal output from the image sensor chip. The memory chip is electrically connected to the image sensor chip through a conductive wire and stores at least one of the pixel signal from the image sensor chip or a pixel signal processed by the logic chip. The memory chip receives the pixel signal output from the image sensor chip through the conductive wire and receives the pixel signal processed by the logic chip through the image sensor chip and the conductive wire.

公开(公告)号：US20160013091A1

公开(公告)日：2016-01-14

申请号：US14723642

申请日：2015-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-hwang Kim ,  Un-byoung Kang ,  Cha-jea Jo ,  Tae-je Cho

IPC: H01L21/768 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L21/486 ,  H01L21/563 ,  H01L23/147 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/17 ,  H01L24/32 ,  H01L24/81 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A method of manufacturing a semiconductor package includes forming a bonding layer on a carrier substrate, bonding an inner substrate to the carrier substrate, removing the carrier substrate, and forming a gap-filling portion by removing a portion of the bonding layer to expose a portion of a solder ball provided in the inner substrate. The inner substrate may be mounted on a package substrate and a semiconductor chip may be mounted on the inner substrate.

Abstract translation: 一种半导体封装的制造方法，其特征在于，在载体基板上形成接合层，将内部基板与载体基板接合，除去载体基板，通过除去接合层的一部分而形成间隙填充部， 设置在内部基板中的焊球。 内部基板可以安装在封装基板上，半导体芯片可以安装在内部基板上。

公开(公告)号：US11637140B2

公开(公告)日：2023-04-25

申请号：US17202702

申请日：2021-03-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji-hwang Kim ,  Jong-bo Shim ,  Sang-uk Han ,  Cha-jea Jo ,  Won-il Lee

IPC: H01L27/146

Abstract: An image sensor package includes an image sensor chip on a package substrate, a logic chip on the package substrate and perpendicularly overlapping the image sensor chip, and a memory chip on the package substrate and perpendicularly overlapping the image sensor chip and logic chip. The logic chip processes a pixel signal output from the image sensor chip. The memory chip is electrically connected to the image sensor chip through a conductive wire and stores at least one of the pixel signal from the image sensor chip or a pixel signal processed by the logic chip. The memory chip receives the pixel signal output from the image sensor chip through the conductive wire and receives the pixel signal processed by the logic chip through the image sensor chip and the conductive wire.

公开(公告)号：US10083939B2

公开(公告)日：2018-09-25

申请号：US15421386

申请日：2017-01-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-kyoung Seo ,  Cha-jea Jo ,  Soo-hyun Ha

IPC: H01L29/40 ,  H01L25/065 ,  H01L23/532 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L23/3185 ,  H01L23/53238 ,  H01L2224/16145 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06582

Abstract: A semiconductor package includes: a first semiconductor chip in which a through-electrode is provided; a second semiconductor chip connected to a top surface of the first semiconductor chip; a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer; and a second connection bump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.

公开(公告)号：US11610865B2

公开(公告)日：2023-03-21

申请号：US17213715

申请日：2021-03-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-kyoung Seo ,  Cha-jea Jo ,  Soo-hyun Ha

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/532

Abstract: A semiconductor package includes a first semiconductor chip in which a through-electrode is provided, a second semiconductor chip connected to a top surface of the first semiconductor chip, a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer, and a second connection bump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.

公开(公告)号：US10658341B2

公开(公告)日：2020-05-19

申请号：US16448703

申请日：2019-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-kyoung Seo ,  Cha-jea Jo ,  Soo-hyun Ha

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/532

Abstract: A semiconductor package includes: a first semiconductor chip in which a through-electrode is provided; a second semiconductor chip connected to a top surface of the first semiconductor chip; a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer, and a second connection hump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.