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公开(公告)号：US10083939B2
公开(公告)日：2018-09-25
申请号：US15421386
申请日：2017-01-31
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sun-kyoung Seo , Cha-jea Jo , Soo-hyun Ha
IPC: H01L29/40 , H01L25/065 , H01L23/532 , H01L23/31
CPC classification number: H01L25/0657 , H01L23/3185 , H01L23/53238 , H01L2224/16145 , H01L2224/73204 , H01L2224/94 , H01L2225/06513 , H01L2225/06517 , H01L2225/06544 , H01L2225/06582
Abstract: A semiconductor package includes: a first semiconductor chip in which a through-electrode is provided; a second semiconductor chip connected to a top surface of the first semiconductor chip; a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer; and a second connection bump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.
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2.发明申请公开(公告)号：US20170084561A1
公开(公告)日：2017-03-23
申请号：US15262040
申请日：2016-09-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sun-kyoung Seo , Seung-kwan Ryu , Ju-il Choi , Tae-je Cho , Yong-hwan Kwon
IPC: H01L23/00
CPC classification number: H01L24/13 , H01L24/05 , H01L24/11 , H01L24/16 , H01L24/81 , H01L2224/02205 , H01L2224/02215 , H01L2224/0345 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05008 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05184 , H01L2224/05569 , H01L2224/05572 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05664 , H01L2224/05666 , H01L2224/05671 , H01L2224/05684 , H01L2224/10145 , H01L2224/11462 , H01L2224/1147 , H01L2224/11614 , H01L2224/1162 , H01L2224/11849 , H01L2224/13006 , H01L2224/13014 , H01L2224/13017 , H01L2224/13018 , H01L2224/13022 , H01L2224/13026 , H01L2224/13076 , H01L2224/13083 , H01L2224/13084 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/1312 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13157 , H01L2224/13164 , H01L2224/13169 , H01L2224/13564 , H01L2224/16227 , H01L2224/16237 , H01L2224/73204 , H01L2224/81011 , H01L2224/81191 , H01L2224/81815 , H01L2924/05042 , H01L2924/05442 , H01L2924/07025 , H01L2924/00014 , H01L2924/014 , H01L2924/01082 , H01L2924/01083 , H01L2924/0103 , H01L2924/01047 , H01L2924/01029 , H01L2924/00012
Abstract: An electronic device is provided, which includes a substrate having an electrically conductive contact pad thereon and an electrically conductive connection terminal on the contact pad. The connection terminal includes an electrically conductive pillar structure and a solder layer that extends on the pillar structure and contacts a protruding portion of a sidewall of the pillar structure. The pillar structure can include a lower pillar layer, a diffusion barrier layer on the lower pillar layer and an upper pillar layer on the diffusion barrier layer. In some additional embodiments of the invention, the protruding portion of the sidewall of the pillar structure includes an outermost portion of an upper surface of the diffusion barrier layer. This can be achieved by making a width of the diffusion barrier layer greater than a width of the upper pillar layer when viewed in transverse cross-section.
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3.发明授权公开(公告)号：US09376541B2
公开(公告)日：2016-06-28
申请号：US14288997
申请日：2014-05-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Un-byoung Kang , Kyung-wook Paik , Tae-Je Cho , Young-kun Jee , Sun-kyoung Seo , Yong-won Choi , Ji-won Shin
IPC: H01L23/29 , C08K3/08 , H01L25/065 , H01L23/00
CPC classification number: C08K3/08 , C08K2003/0893 , C08K2201/011 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/91 , H01L25/0657 , H01L2224/0401 , H01L2224/0557 , H01L2224/05647 , H01L2224/05655 , H01L2224/1134 , H01L2224/13111 , H01L2224/16145 , H01L2224/16146 , H01L2224/16503 , H01L2224/17181 , H01L2224/2732 , H01L2224/27436 , H01L2224/2929 , H01L2224/29318 , H01L2224/32505 , H01L2224/33181 , H01L2224/48091 , H01L2224/48227 , H01L2224/73104 , H01L2224/73204 , H01L2224/73207 , H01L2224/73215 , H01L2224/81191 , H01L2224/81203 , H01L2224/81815 , H01L2224/9211 , H01L2224/94 , H01L2224/97 , H01L2924/15311 , H01L2924/3651 , H01L2924/00014 , H01L2924/0665 , H01L2924/00012 , H01L2224/27 , H01L2224/11 , H01L2224/81 , H01L2224/83 , H01L2924/01047 , H01L2924/01029 , H01L2224/8211
Abstract: A non-conductive material layer, selected from a non-conductive film and a non-conductive polymer paste, and containing a dispersion of zinc (Zn) particles is disclosed, together with semiconductor packages including the non-conductive material layer. The non-conductive material layer contains zinc (Zn) particles having an average particle diameter of about 1 nm to about 200 nm in a non-conductive polymer base material of a film type, and a semiconductor package includes the non-conductive film. By using the non-conductive film and/or the non-conductive paste containing the zinc dispersion, e a semiconductor package having excellent electric connection properties and high reliability may be manufactured through simple processes at low manufacturing costs.
Abstract translation: 公开了一种选自非导电膜和非导电聚合物浆料并含有锌（Zn）颗粒的分散体的非导电材料层以及包括非导电材料层的半导体封装。 非导电材料层在薄膜型非导电性聚合物基材中含有平均粒径为约1nm〜约200nm的锌（Zn）颗粒，半导体封装包括非导电膜。 通过使用含有锌分散体的非导电性膜和/或非导电性糊剂，可以以低制造成本通过简单的工艺制造具有优异的电连接性能和高可靠性的半导体封装。
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公开(公告)号：US10991677B2
公开(公告)日：2021-04-27
申请号：US16847987
申请日：2020-04-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sun-kyoung Seo , Cha-jea Jo , Soo-hyun Ha
IPC: H01L25/065 , H01L23/31 , H01L23/532
Abstract: A semiconductor package includes: a first semiconductor chip in which a through-electrode is provided; a second semiconductor chip connected to a top surface of the first semiconductor chip; a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer, and a second connection hump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.
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公开(公告)号：US10373935B2
公开(公告)日：2019-08-06
申请号：US16114795
申请日：2018-08-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sun-kyoung Seo , Cha-jea Jo , Soo-hyun Ha
IPC: H01L23/31 , H01L23/532 , H01L25/065
Abstract: A semiconductor package includes: a first semiconductor chip in which a through-electrode is provided; a second semiconductor chip connected to a top surface of the first semiconductor chip; a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer; and a second connection bump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.
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Patent Agency Ranking
公开(公告)号：US10134702B2
公开(公告)日：2018-11-20
申请号：US15494942
申请日：2017-04-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sun-kyoung Seo , Seung-kwan Ryu , Cha-jea Jo , Tae-Je Cho
IPC: H01L25/065 , H01L23/00 , H01L23/48
Abstract: The semiconductor chip including a semiconductor device layer including a pad region and a cell region, a plurality of uppermost wirings formed on the semiconductor device layer to be arranged at an equal distance in the cell region, a passivation layer formed in the cell region and the pad region, and a plurality of thermal bumps disposed on the passivation layer to be electrically insulated from the plurality of uppermost wirings may be provided. The semiconductor device layer may include a plurality of through silicon via (TSV) structures in the pad region. The plurality of uppermost wirings may extend in parallel along one direction and have a same width. The passivation layer may cover at least a top surface of the plurality of uppermost wirings in the cell region and includes a top surface having a wave shape.
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公开(公告)号：US11610865B2
公开(公告)日：2023-03-21
申请号：US17213715
申请日：2021-03-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sun-kyoung Seo , Cha-jea Jo , Soo-hyun Ha
IPC: H01L25/065 , H01L23/31 , H01L23/532
Abstract: A semiconductor package includes a first semiconductor chip in which a through-electrode is provided, a second semiconductor chip connected to a top surface of the first semiconductor chip, a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer, and a second connection bump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.
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公开(公告)号：US10658341B2
公开(公告)日：2020-05-19
申请号：US16448703
申请日：2019-06-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sun-kyoung Seo , Cha-jea Jo , Soo-hyun Ha
IPC: H01L25/065 , H01L23/31 , H01L23/532
Abstract: A semiconductor package includes: a first semiconductor chip in which a through-electrode is provided; a second semiconductor chip connected to a top surface of the first semiconductor chip; a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer, and a second connection hump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.
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公开(公告)号：US10008462B2
公开(公告)日：2018-06-26
申请号：US15226231
申请日：2016-08-02
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sun-kyoung Seo , Tae-je Cho , Yong-hwan Kwon , Hyung-gil Baek , Hyun-soo Chung , Seung-kwan Ryu , Myeong-soon Park
CPC classification number: H01L24/08 , H01L23/291 , H01L23/3171 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/94 , H01L2224/02311 , H01L2224/02321 , H01L2224/0235 , H01L2224/02351 , H01L2224/0236 , H01L2224/0239 , H01L2224/0345 , H01L2224/03452 , H01L2224/03614 , H01L2224/03912 , H01L2224/0401 , H01L2224/05008 , H01L2224/05011 , H01L2224/05012 , H01L2224/05014 , H01L2224/05015 , H01L2224/05017 , H01L2224/05082 , H01L2224/05124 , H01L2224/05147 , H01L2224/05558 , H01L2224/05582 , H01L2224/05611 , H01L2224/05639 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05684 , H01L2224/08058 , H01L2224/11462 , H01L2224/1147 , H01L2224/11849 , H01L2224/119 , H01L2224/13006 , H01L2224/13082 , H01L2224/13083 , H01L2224/131 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/94 , H01L2924/19105 , H01L2224/11 , H01L2924/00014 , H01L2924/00012 , H01L2924/014 , H01L2924/01047 , H01L2924/01029 , H01L2924/01046 , H01L2924/01083 , H01L2924/01051 , H01L2224/034 , H01L2224/1146 , H01L2224/0361 , H01L2924/01028 , H01L2924/01079 , H01L2924/01024 , H01L2924/01022
Abstract: A semiconductor package includes a semiconductor substrate and an electrode pad formed on the semiconductor substrate. The electrode pad includes a central portion and a peripheral portion, and a first pattern is located on the peripheral portion. A passivation layer is formed on the semiconductor substrate and the electrode pad. The passivation layer has an opening exposing the central portion of the electrode pad and a second pattern located on the first pattern. A seed layer is formed on the electrode pad and the passivation layer. The seed layer has a third pattern formed on the second pattern. A bump is formed on the seed layer and electrically connected to the electrode pad. An undercut is formed around the third pattern located under an edge of a lower portion of the bump.
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10.发明授权公开(公告)号：US09831202B2
公开(公告)日：2017-11-28
申请号：US15262040
申请日：2016-09-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sun-kyoung Seo , Seung-kwan Ryu , Ju-il Choi , Tae-je Cho , Yong-hwan Kwon
CPC classification number: H01L24/13 , H01L24/05 , H01L24/11 , H01L24/16 , H01L24/81 , H01L2224/02205 , H01L2224/02215 , H01L2224/0345 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05008 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05184 , H01L2224/05569 , H01L2224/05572 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05664 , H01L2224/05666 , H01L2224/05671 , H01L2224/05684 , H01L2224/10145 , H01L2224/11462 , H01L2224/1147 , H01L2224/11614 , H01L2224/1162 , H01L2224/11849 , H01L2224/13006 , H01L2224/13014 , H01L2224/13017 , H01L2224/13018 , H01L2224/13022 , H01L2224/13026 , H01L2224/13076 , H01L2224/13083 , H01L2224/13084 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/1312 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13157 , H01L2224/13164 , H01L2224/13169 , H01L2224/13564 , H01L2224/16227 , H01L2224/16237 , H01L2224/73204 , H01L2224/81011 , H01L2224/81191 , H01L2224/81815 , H01L2924/05042 , H01L2924/05442 , H01L2924/07025 , H01L2924/00014 , H01L2924/014 , H01L2924/01082 , H01L2924/01083 , H01L2924/0103 , H01L2924/01047 , H01L2924/01029 , H01L2924/00012
Abstract: An electronic device is provided, which includes a substrate having an electrically conductive contact pad thereon and an electrically conductive connection terminal on the contact pad. The connection terminal includes an electrically conductive pillar structure and a solder layer that extends on the pillar structure and contacts a protruding portion of a sidewall of the pillar structure. The pillar structure can include a lower pillar layer, a diffusion barrier layer on the lower pillar layer and an upper pillar layer on the diffusion barrier layer. In some additional embodiments of the invention, the protruding portion of the sidewall of the pillar structure includes an outermost portion of an upper surface of the diffusion barrier layer. This can be achieved by making a width of the diffusion barrier layer greater than a width of the upper pillar layer when viewed in transverse cross-section.
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