TEST BOARD AND TEST METHOD FOR SEMICONDUCTOR DEVICE USING THE SAME

    公开(公告)号:US20240077535A1

    公开(公告)日:2024-03-07

    申请号:US18300870

    申请日:2023-04-14

    CPC classification number: G01R31/31924 G01R31/2834 G01R31/31905

    Abstract: Disclosed is a test board which includes a substrate that includes a device under test (DUT) placement area where a first DUT and a second DUT are disposed, a first load switch connected in series with the first DUT and configured to be set to a switch on state or a switch off state based on a first enable signal, a second load switch connected in series with the second DUT and configured to be set to the switch on state or the switch off state depending on a second enable signal, and a test controller. The test controller may be configured to perform a test operation in a (1-1)-th mode by activating the first enable signal and deactivating the second enable signal and then perform the test operation in a (1-2)-th mode by deactivating the first enable signal and activating the second enable signal.

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