公开(公告)号：US09971721B2

公开(公告)日：2018-05-15

申请号：US14824476

申请日：2015-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ilhyun Cho ,  Soonwan Kwon ,  Kibeom Kim ,  Rakie Kim

IPC: G06F13/40 ,  G06F3/01 ,  G06F1/32 ,  G06F3/023 ,  G06F3/0488

CPC classification number: G06F13/4022 ,  G06F1/3215 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3296 ,  G06F3/023 ,  G06F3/04886 ,  Y02D10/126 ,  Y02D10/151 ,  Y02D10/152 ,  Y02D10/172

Abstract: A method for controlling performance of an electronic device is provided. The method includes sensing user input, predicting user input speed, and controlling at least one processing unit of the electronic device based on a predicted user input speed and performance assignment information. Here, the performance assignment information includes control information mapped respectively with user input speeds for controlling the at least one processing unit of the electronic device.

公开(公告)号：US11836463B2

公开(公告)日：2023-12-05

申请号：US17106266

申请日：2020-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minje Kim ,  Soonwan Kwon

IPC: G06F7/544 ,  G06G7/16 ,  G06F9/30 ,  G06F7/57 ,  G06N3/063

CPC classification number: G06F7/5443 ,  G06F7/57 ,  G06F9/3001 ,  G06G7/16 ,  G06N3/063

Abstract: A neural network device includes a shift register circuit, a control circuit, and a processing circuit. The shift register circuit includes registers configured to, in each cycle of cycles, transfer stored data to a next register and store new data received from a previous register to a current register. The control circuit is configured to sequentially input data of input activations included in an input feature map into the shift register circuit in a preset order. The processing circuit, includes crossbar array groups that receive input activations from at least one of the registers and perform a multiply-accumulate (MAC) operation with respect to the received input activation and weights, is configured to accumulate and add at least some operation results output from the crossbar array groups in a preset number of cycles to obtain an output activation in an output feature map.

公开(公告)号：US20220019408A1

公开(公告)日：2022-01-20

申请号：US17106266

申请日：2020-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minje Kim ,  Soonwan Kwon

IPC: G06F7/544 ,  G06N3/063 ,  G06F7/57 ,  G06F9/30

Abstract: A neural network device includes a shift register circuit, a control circuit, and a processing circuit. The shift register circuit includes registers configured to, in each cycle of cycles, transfer stored data to a next register and store new data received from a previous register to a current register. The control circuit is configured to sequentially input data of input activations included in an input feature map into the shift register circuit in a preset order. The processing circuit, includes crossbar array groups that receive input activations from at least one of the registers and perform a multiply-accumulate (MAC) operation with respect to the received input activation and weights, is configured to accumulate and add at least some operation results output from the crossbar array groups in a preset number of cycles to obtain an output activation in an output feature map.