公开(公告)号：US20250118671A1

公开(公告)日：2025-04-10

申请号：US18643761

申请日：2024-04-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Su Hyun Bark ,  Jun Sung Kim ,  Kyeong Beom Park ,  Jong Min Baek

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A semiconductor device includes a substrate; an interlayer insulating layer disposed on the substrate; an upper wiring trench disposed in the interlayer insulating layer; and an upper wiring layer including: an upper wiring barrier layer disposed along a sidewall and a bottom surface of the upper wiring trench, an upper wiring filling layer disposed on the upper wiring barrier layer so as to fill at least a portion of an inside of the upper wiring trench, and an upper wiring capping layer disposed on an upper surface of the upper wiring filling layer, wherein the upper wiring capping layer includes cobalt (Co), and wherein a volume percentage of a crystal structure having a hexagonal close-packed structure included in the upper wiring capping layer is in a range of about 80% to about 100%.

公开(公告)号：US10535600B2

公开(公告)日：2020-01-14

申请号：US15987211

申请日：2018-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoon Seok Seo ,  Jong Min Baek ,  Su Hyun Bark ,  Sang Hoon Ahn ,  Hyeok Sang Oh ,  Eui Bok Lee

IPC: H01L23/52 ,  H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L29/41

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including a lower wiring, a first interlayer insulating film disposed on the substrate and including a first region and a second region over the first region, an etch stop film on the first interlayer insulating film, a second interlayer insulating film on the etch stop film, a first upper wiring in the second interlayer insulating film, the etch stop film, and the second region of the first interlayer insulating film and the first upper wiring is spaced apart from the lower wiring and a via in the first region of the first interlayer insulating film, and the via connects the lower wiring and the first upper wiring, wherein the first upper wiring includes a first portion in the second interlayer insulating film, and a second portion in the etch stop film and the second region of the first interlayer insulating film, and a sidewall of the second portion of the first upper wiring includes a stepwise shape.

公开(公告)号：US10950541B2

公开(公告)日：2021-03-16

申请号：US16441042

申请日：2019-06-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soon Gyu Hwang ,  Kyoung Woo Lee ,  YoungWoo Cho ,  Il Sup Kim ,  Su Hyun Bark ,  Young-Ju Park ,  Jong Min Baek ,  Min Huh

IPC: H01L23/48 ,  H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: A semiconductor device includes a substrate, a first lower wiring line on the substrate, a first insulation layer on the first lower wiring line, a first dielectric barrier layer and a first etch stop layer sequentially stacked on the first insulation layer, a second insulation layer on the first etch stop layer, a first upper wiring line extending through the second insulation layer, the first etch stop layer, and the first dielectric barrier layer, and a first conductive via in the first insulation layer and electrically connecting the first lower wiring line and the first upper wiring line. An upper surface of the first conductive via protrudes above a lower surface of the first upper wiring line.

公开(公告)号：US10475739B2

公开(公告)日：2019-11-12

申请号：US15840128

申请日：2017-12-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woo Kyung You ,  Eui Bok Lee ,  Jong Min Baek ,  Su Hyun Bark ,  Jang Ho Lee ,  Sang Hoon Ahn ,  Hyeok Sang Oh

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate comprising a lower wire, an etch stop layer on the substrate, an interlayer insulating layer on the etch stop layer, an upper wire disposed in the interlayer insulating layer and separated from the lower wire and a via formed in the interlayer insulating layer and the etch stop layer and connecting the lower wire with the upper wire, wherein the via comprises a first portion in the etch stop layer and a second portion in the interlayer insulating layer, and wherein a sidewall of the first portion of the via increases stepwise.