公开(公告)号：US20220182513A1

公开(公告)日：2022-06-09

申请号：US17534958

申请日：2021-11-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwoo KIM ,  Sujin JUNG ,  Seungkwon CHOI ,  Kyoungjong KIM

IPC: H04N5/225

Abstract: An electronic device is provided. The electronic device includes a housing including a support member and a rear plate, a camera support member disposed between the support member and the rear plate, a camera module disposed on the support member, a camera window covering at least a part of the camera module, and a compression member disposed between the camera window and the camera module. The camera module may include a first area facing the camera support member, a second area facing the compression member, and a third area facing the camera window and at least partially surrounded by the compression member.

公开(公告)号：US20220115514A1

公开(公告)日：2022-04-14

申请号：US17559347

申请日：2021-12-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sujin JUNG ,  Kihwan KIM ,  Sunguk JANG ,  Youngdae CHO

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/08

Abstract: A semiconductor device including: an active pattern on a substrate, the active pattern including a recess, the recess having a “V” shape; a growth prevention pattern on the recess; gate structures on portions of the active pattern at opposite sides of the recess; channels spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate, each of the channels extending through one of the gate structures; and a source/drain layer on the growth prevention pattern, the source/drain layer contacting the channels.

公开(公告)号：US20200053444A1

公开(公告)日：2020-02-13

申请号：US16535569

申请日：2019-08-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwoo KIM ,  Sujin JUNG ,  Youngjin CHO ,  Sungjin PARK ,  Hyunmin OH ,  lksu JUNG

IPC: H04R1/02 ,  H05K7/20 ,  H04R1/40 ,  H04R3/12 ,  H04R1/24 ,  H04R1/04

Abstract: An electronic device is provided. The electronic device includes a housing including a first plate and at least one first opening; and a speaker structure spaced apart from the first plate and disposed in the housing, wherein the speaker structure includes a first structure which faces in a first direction, opposes the first plate, and forms a space connecting to the at least one first opening along with the first plate; a second opening formed by penetrating through a part of the first structure; at least one component disposed in the speaker structure and emitting heat; a thermal conducting member including a first portion disposed in the speaker structure and being in contact with the at least one component, and a second portion disposed in the second opening; and at least one speaker disposed in a direction different from the first direction.

公开(公告)号：US20160359021A1

公开(公告)日：2016-12-08

申请号：US15134556

申请日：2016-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： JinBum KIM ,  Kang Hun MOON ,  Choeun LEE ,  Sujin JUNG ,  Yang XU

IPC: H01L29/66 ,  H01L29/08 ,  H01L21/306 ,  H01L29/06 ,  H01L21/308 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/66795 ,  H01L21/823425 ,  H01L21/823431 ,  H01L29/0657 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7848

Abstract: Methods of forming an integrated circuit device are provided. The methods may include forming a gate structure on a substrate, forming a first etch mask on a sidewall of the gate structure, anisotropically etching the substrate using the gate structure and the first etch mask as an etch mask to form a preliminary recess in the substrate, forming a sacrificial layer in the preliminary recess, forming a second etch mask on the first etch mask, etching the sacrificial layer and the substrate beneath the sacrificial layer using the gate structure and the first and second etch masks as an etch mask to form a source/drain recess in the substrate, and forming a source/drain in the source/drain recess. A sidewall of the source/drain recess may be recessed toward the gate structure relative to an outer surface of the second etch mask.

Abstract translation: 提供了形成集成电路器件的方法。 所述方法可以包括在衬底上形成栅极结构，在栅极结构的侧壁上形成第一蚀刻掩模，使用栅极结构和第一蚀刻掩模各向异性蚀刻衬底作为蚀刻掩模，以在衬底中形成预备凹槽 在所述初步凹槽中形成牺牲层，在所述第一蚀刻掩模上形成第二蚀刻掩模，使用所述栅极结构和所述第一和第二蚀刻掩模作为蚀刻掩模蚀刻所述牺牲层和所述牺牲层下方的所述衬底，以形成 源极/漏极凹部，并且在源极/漏极凹部中形成源极/漏极。 源极/漏极凹部的侧壁可以相对于第二蚀刻掩模的外表面朝向栅极结构凹陷。

公开(公告)号：US20240334031A1

公开(公告)日：2024-10-03

申请号：US18742429

申请日：2024-06-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwoo KIM ,  Sujin JUNG ,  Seungkwon CHOI ,  Kyoungjong KIM

IPC: H04N23/51 ,  H04N23/55 ,  H04N23/57

CPC classification number: H04N23/51 ,  H04N23/55 ,  H04N23/57

Abstract: An electronic device is provided. The electronic device includes a housing including a support member and a rear plate, a camera support member disposed between the support member and the rear plate, a camera module disposed on the support member, a camera window covering at least a part of the camera module, and a compression member disposed between the camera window and the camera module. The camera module may include a first area facing the camera support member, a second area facing the compression member, and a third area facing the camera window and at least partially surrounded by the compression member.

公开(公告)号：US20240203989A1

公开(公告)日：2024-06-20

申请号：US18227064

申请日：2023-07-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinbum KIM ,  Gyeom KIM ,  Youngkwang KIM ,  Chanyoung KIM ,  Jangwoo PARK ,  Sangmoon LEE ,  Sujin JUNG

IPC: H01L27/092 ,  H01L29/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/161 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L27/092 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/775

Abstract: A semiconductor device includes a substrate including a p-type metal-oxide-semiconductor (MOS) field-effect transistor (FET) (PMOSFET) region and an n-type MOSFET (NMOSFET) region, a first active pattern on the PMOSFET region, a second active pattern on the NMOSFET region, a first channel pattern and a first source/drain pattern on the first active pattern, the first channel pattern connected to the first source/drain pattern, a second channel pattern and a second source/drain pattern provided on the second active pattern, the second channel pattern connected to the second source/drain pattern, and a gate electrode on the first channel pattern and the second channel pattern.

公开(公告)号：US20230100189A1

公开(公告)日：2023-03-30

申请号：US17730928

申请日：2022-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dahye KIM ,  Sujin JUNG ,  Ingyu JANG ,  Jinbum KIM

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/417

Abstract: A semiconductor device includes a fin-type active region that protrudes from a substrate and extends in a first direction, a plurality of channel layers on the fin-type active region that are spaced apart from each other in a second direction that is perpendicular to an upper surface of the substrate, a gate structure that intersects the fin-type active region, extends in the second direction, and surrounds each of the plurality of channel layers in a third direction, fence spacers on side surfaces of the fin-type active region in the second direction on sides of the gate structure and extending in the second direction, and a source/drain region between the fence spacers on the fin-type active region at sides of the gate structure, connected to each of the plurality of channel layers, and having voids in side surfaces adjacent the fence spacers.

公开(公告)号：US20220199618A1

公开(公告)日：2022-06-23

申请号：US17383749

申请日：2021-07-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sujin JUNG ,  Kihwan KIM ,  Sunguk JANG ,  Youngdae CHO

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78

Abstract: An integrated circuit (IC) device includes a fin-type active region extending longitudinally in a first lateral direction on a substrate. A nanosheet is apart from a fin top surface of the fin-type active region in a vertical direction. An inner insulating spacer is between the substrate and the nanosheet. A gate line includes a main gate portion and a sub-gate portion. The main gate portion extends longitudinally in a second lateral direction on the nanosheet. The sub-gate portion is integrally connected to the main gate portion and between the substrate and the nanosheet. A source/drain region is in contact with the inner insulating spacer and the nanosheet. The source/drain region includes a single crystalline semiconductor body and at least one lower stacking fault surface linearly extending from the inner insulating spacer through the single crystalline semiconductor body.

公开(公告)号：US20180151705A1

公开(公告)日：2018-05-31

申请号：US15871479

申请日：2018-01-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： JinBum KIM ,  Kang Hun MOON ,  Choeun LEE ,  Sujin JUNG ,  Yang XU

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/823425 ,  H01L21/823431 ,  H01L29/0657 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7848

Abstract: Methods of forming an integrated circuit device are provided. The methods may include forming a gate structure on a substrate, forming a first etch mask on a sidewall of the gate structure, anisotropically etching the substrate using the gate structure and the first etch mask as an etch mask to form a preliminary recess in the substrate, forming a sacrificial layer in the preliminary recess, forming a second etch mask on the first etch mask, etching the sacrificial layer and the substrate beneath the sacrificial layer using the gate structure and the first and second etch masks as an etch mask to form a source/drain recess in the substrate, and forming a source/drain in the source/drain recess. A sidewall of the source/drain recess may be recessed toward the gate structure relative to an outer surface of the second etch mask.

公开(公告)号：US20230395684A1

公开(公告)日：2023-12-07

申请号：US18130070

申请日：2023-04-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sujin JUNG ,  Jinbum Kim ,  Dahye Kim ,  Ingyu Jang

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/775

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/78696 ,  H01L29/775

Abstract: A semiconductor device is provided. The semiconductor device includes: an active region extending in a first direction on a substrate, a plurality of channel layers spaced apart from each other in a vertical direction, a gate structure enclosing the plurality of channel layers, respectively, and a source/drain region contacting the plurality of channel layers. The source/drain region includes a first epitaxial layer extending to contact the plurality of channel layers, and a second epitaxial layer on the first epitaxial layer. A surface in which the first epitaxial layer and the second epitaxial layer contact each other includes: first surfaces having a first slope; second surfaces having a second slope, different from the first slope; first bent portions between the first surfaces and the second surfaces; and a second bent portion in which the second surfaces meet.