公开(公告)号：US20210104483A1

公开(公告)日：2021-04-08

申请号：US16885748

申请日：2020-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinduck Park ,  Chansik Kwon ,  Jongkeun Moon ,  Suyang Lee

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/31

Abstract: Semiconductor packages may include a first semiconductor chip including a first through-electrode and a first upper connection pad and on an upper surface of the first semiconductor chip, a second semiconductor chip on the first semiconductor chip and including a second lower connection pad on a lower surface of the second semiconductor chip, a connection bump between the first and second semiconductor chips and connected to the first upper connection pad and the second lower connection pad, a first insulating layer between the first and second semiconductor chips and surrounding the first upper connection pad, the connection bump, and the second lower connection pad, and a second insulating layer between the first semiconductor chip and the first insulating layer and extending on the upper surface of the first semiconductor chip, a side surface of the first upper connection pad, and a portion of a side surface of the connection bump.

公开(公告)号：US11676923B2

公开(公告)日：2023-06-13

申请号：US16885748

申请日：2020-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinduck Park ,  Chansik Kwon ,  Jongkeun Moon ,  Suyang Lee

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L24/13 ,  H01L23/3121 ,  H01L25/0657 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06541

Abstract: Semiconductor packages may include a first semiconductor chip including a first through-electrode and a first upper connection pad and on an upper surface of the first semiconductor chip, a second semiconductor chip on the first semiconductor chip and including a second lower connection pad on a lower surface of the second semiconductor chip, a connection bump between the first and second semiconductor chips and connected to the first upper connection pad and the second lower connection pad, a first insulating layer between the first and second semiconductor chips and surrounding the first upper connection pad, the connection bump, and the second lower connection pad, and a second insulating layer between the first semiconductor chip and the first insulating layer and extending on the upper surface of the first semiconductor chip, a side surface of the first upper connection pad, and a portion of a side surface of the connection bump.