公开(公告)号：US11474149B2

公开(公告)日：2022-10-18

申请号：US16916679

申请日：2020-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chansik Kwon ,  Junyoung Ko ,  Jongkeun Moon ,  Jinduck Park ,  Jiyeon Han

IPC: G01R31/26 ,  G01R31/28 ,  H01L21/66

Abstract: A test apparatus includes a test chamber in which a plurality of the semiconductor packages having a plurality of component dies is secured, an operation tester configured to conduct an operation test to the plurality of semiconductor packages to detect whether at least one semiconductor package is an operation fault package having a fault and identify a fault package point at which the operation fault package is located, a fault heat detector configured to detect a fault heat generated from the fault, and a test controller configured to control the operation tester to conduct the operation test to the plurality of semiconductor packages and control the fault heat detector subsequent to the operation test to detect the fault heat generated from the fault of the operation fault package to determine a vertical point of the fault and to determine a fault die having the fault.

公开(公告)号：US20240047328A1

公开(公告)日：2024-02-08

申请号：US18341345

申请日：2023-06-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinduck Park ,  Chansik Kwon ,  Yongseong Kim ,  Inwook Im ,  Jiyeon Han

IPC: H01L23/498 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49822 ,  H01L25/0657 ,  H01L23/3107 ,  H01L23/49838 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15153 ,  H01L2924/15184

Abstract: A semiconductor package includes a package base substrate including a substrate cavity formed therein, the substrate cavity extending from a top surface of the package base substrate downwardly toward a bottom surface of the package base substrate. The package base substrate further includes a plurality of base insulating layers, a plurality of substrate wiring patterns extending along at least one of a top surface and a bottom surface of each of the plurality of base insulating layers, and a plurality of substrate conductive vias which pass through at least one of the plurality of base insulating layers and are connected to the plurality of substrate wiring patterns. The semiconductor package further includes a plurality of semiconductor chips disposed at a bottom of the substrate cavity and stacked in a direction perpendicular to a plane of the package base substrate.

公开(公告)号：US20210104483A1

公开(公告)日：2021-04-08

申请号：US16885748

申请日：2020-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinduck Park ,  Chansik Kwon ,  Jongkeun Moon ,  Suyang Lee

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/31

Abstract: Semiconductor packages may include a first semiconductor chip including a first through-electrode and a first upper connection pad and on an upper surface of the first semiconductor chip, a second semiconductor chip on the first semiconductor chip and including a second lower connection pad on a lower surface of the second semiconductor chip, a connection bump between the first and second semiconductor chips and connected to the first upper connection pad and the second lower connection pad, a first insulating layer between the first and second semiconductor chips and surrounding the first upper connection pad, the connection bump, and the second lower connection pad, and a second insulating layer between the first semiconductor chip and the first insulating layer and extending on the upper surface of the first semiconductor chip, a side surface of the first upper connection pad, and a portion of a side surface of the connection bump.

公开(公告)号：US11676923B2

公开(公告)日：2023-06-13

申请号：US16885748

申请日：2020-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinduck Park ,  Chansik Kwon ,  Jongkeun Moon ,  Suyang Lee

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L24/13 ,  H01L23/3121 ,  H01L25/0657 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06541

Abstract: Semiconductor packages may include a first semiconductor chip including a first through-electrode and a first upper connection pad and on an upper surface of the first semiconductor chip, a second semiconductor chip on the first semiconductor chip and including a second lower connection pad on a lower surface of the second semiconductor chip, a connection bump between the first and second semiconductor chips and connected to the first upper connection pad and the second lower connection pad, a first insulating layer between the first and second semiconductor chips and surrounding the first upper connection pad, the connection bump, and the second lower connection pad, and a second insulating layer between the first semiconductor chip and the first insulating layer and extending on the upper surface of the first semiconductor chip, a side surface of the first upper connection pad, and a portion of a side surface of the connection bump.