公开(公告)号：US20180102428A1

公开(公告)日：2018-04-12

申请号：US15613955

申请日：2017-06-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYUNGIN CHOI ,  CHANGHWA KIM ,  TAEGON KIM ,  HYUNCHUL SONG

IPC: H01L29/78 ,  H01L29/06

CPC classification number: H01L29/785 ,  H01L29/0649 ,  H01L29/66795

Abstract: Semiconductor devices and methods of forming the semiconductor devices are provided. The semiconductor devices may include a substrate, a device isolation layer that defines an active region, an active fin vertically protruding from the active region of the substrate and extending in a horizontal direction, a gate structure traversing the active fin, and a source/drain contact on the active fin on a side of the gate structure. The gate structure may include a gate pattern and a capping pattern on the gate pattern, and the capping pattern may have impurities doped therein. The capping pattern may include a first part and a second part between the first part and the gate pattern. The first and second parts may have impurity concentrations different from each other.

公开(公告)号：US20210013204A1

公开(公告)日：2021-01-14

申请号：US17015307

申请日：2020-09-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： KYUNGIN CHOI ,  Taehyeon KIM ,  HONGSHIK SHIN ,  TAEGON KIM ,  JAEYOUNG PARK ,  YUICHIRO SASAKI

IPC: H01L27/092 ,  H01L21/225 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417

Abstract: A method of fabricating a semiconductor device includes pattering an upper portion of a substrate to form a first active pattern, the substrate including a semiconductor element having a first lattice constant, performing a selective epitaxial growth process on an upper portion of the first active pattern to form a first source/drain region, doping the first source/drain region with gallium, performing an annealing process on the first source/drain region doped with gallium, and forming a first contact pattern coupled to the first source/drain region. The first source/drain region includes a semiconductor element having a second lattice constant larger than the first lattice constant.

公开(公告)号：US20190287969A1

公开(公告)日：2019-09-19

申请号：US16419318

申请日：2019-05-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： KYUNGIN CHOI ,  Taehyeon KIM ,  HONGSHIK SHIN ,  TAEGON KIM ,  JAEYOUNG PARK ,  YUICHIRO SASAKI

IPC: H01L27/092 ,  H01L21/225 ,  H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

Abstract: A method of fabricating a semiconductor device includes pattering an upper portion of a substrate to form a first active pattern, the substrate including a semiconductor element having a first lattice constant, performing a selective epitaxial growth process on an upper portion of the first active pattern to form a first source/drain region, doping the first source/drain region with gallium, performing an annealing process on the first source/drain region doped with gallium, and forming a first contact pattern coupled to the first source/drain region. The first source/drain region includes a semiconductor element having a second lattice constant larger than the first lattice constant.

公开(公告)号：US20230411451A1

公开(公告)日：2023-12-21

申请号：US18182435

申请日：2023-03-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEUNG MO KANG ,  TAEGON KIM ,  JAEMUN KIM ,  JAEHOON OH ,  SUNHYE LEE ,  SIHYUNG LEE ,  JURI LEE

IPC: H01L29/06 ,  H01L21/762 ,  H01L21/02 ,  H01L21/768 ,  H01L29/423

CPC classification number: H01L29/0653 ,  H01L21/76224 ,  H01L21/02164 ,  H01L21/76829 ,  H01L29/42392

Abstract: A semiconductor device may include a first active pattern and a second active pattern on a substrate, a device isolation layer in a trench between the first active pattern and the second active pattern, a first channel pattern and a second channel pattern provided on the first active pattern and the second active pattern, respectively, each of the first channel pattern and the second channel pattern including a plurality of stacked semiconductor patterns, and a gate electrode on the first channel pattern and the second channel pattern. The device isolation layer may include a first portion and a second portion which are vertically overlapped with the gate electrode. The first portion may be provided on the second portion. A silicon concentration of the first portion may be higher than a silicon concentration of the second portion.

公开(公告)号：US20180286861A1

公开(公告)日：2018-10-04

申请号：US15793442

申请日：2017-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： KYUNGIN CHOI ,  Taehyeon KIM ,  HONGSHIK SHIN ,  TAEGON KIM ,  JAEYOUNG PARK ,  YUICHIRO SASAKI

IPC: H01L27/092 ,  H01L21/768 ,  H01L21/225

CPC classification number: H01L27/0922 ,  H01L21/2253 ,  H01L21/76841 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/161 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/785

Abstract: A method of fabricating a semiconductor device includes pattering an upper portion of a substrate to form a first active pattern, the substrate including a semiconductor element having a first lattice constant, performing a selective epitaxial growth process on an upper portion of the first active pattern to form a first source/drain region, doping the first source/drain region with gallium, performing an annealing process on the first source/drain region doped with gallium, and forming a first contact pattern coupled to the first source/drain region. The first source/drain region includes a semiconductor element having a second lattice constant larger than the first lattice constant.