公开(公告)号：US20190057966A1

公开(公告)日：2019-02-21

申请号：US15869227

申请日：2018-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： HONG-SHIK SHIN ,  TAE-GON KIM ,  YUICHIRO SASAKI

IPC: H01L27/092 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78 ,  H01L29/167 ,  H01L29/06 ,  H01L29/165 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/66 ,  H01L21/265 ,  H01L21/266

Abstract: A semiconductor device includes: a substrate including a field region that defines an active region; source/drain regions in the active region; a channel region between the source/drain regions; a lightly doped drain (LDD) region between one of the source/drain regions and the channel region; and a gate structure disposed on the channel region. An upper portion of the active region may include an epitaxial growth layer having a larger lattice constant than silicon (Si), and the source/drain regions and the LDD region may be doped with gallium (Ga).

公开(公告)号：US20180286861A1

公开(公告)日：2018-10-04

申请号：US15793442

申请日：2017-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： KYUNGIN CHOI ,  Taehyeon KIM ,  HONGSHIK SHIN ,  TAEGON KIM ,  JAEYOUNG PARK ,  YUICHIRO SASAKI

IPC: H01L27/092 ,  H01L21/768 ,  H01L21/225

CPC classification number: H01L27/0922 ,  H01L21/2253 ,  H01L21/76841 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/161 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/785

Abstract: A method of fabricating a semiconductor device includes pattering an upper portion of a substrate to form a first active pattern, the substrate including a semiconductor element having a first lattice constant, performing a selective epitaxial growth process on an upper portion of the first active pattern to form a first source/drain region, doping the first source/drain region with gallium, performing an annealing process on the first source/drain region doped with gallium, and forming a first contact pattern coupled to the first source/drain region. The first source/drain region includes a semiconductor element having a second lattice constant larger than the first lattice constant.

公开(公告)号：US20210013204A1

公开(公告)日：2021-01-14

申请号：US17015307

申请日：2020-09-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： KYUNGIN CHOI ,  Taehyeon KIM ,  HONGSHIK SHIN ,  TAEGON KIM ,  JAEYOUNG PARK ,  YUICHIRO SASAKI

IPC: H01L27/092 ,  H01L21/225 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417

Abstract: A method of fabricating a semiconductor device includes pattering an upper portion of a substrate to form a first active pattern, the substrate including a semiconductor element having a first lattice constant, performing a selective epitaxial growth process on an upper portion of the first active pattern to form a first source/drain region, doping the first source/drain region with gallium, performing an annealing process on the first source/drain region doped with gallium, and forming a first contact pattern coupled to the first source/drain region. The first source/drain region includes a semiconductor element having a second lattice constant larger than the first lattice constant.

公开(公告)号：US20190287969A1

公开(公告)日：2019-09-19

申请号：US16419318

申请日：2019-05-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： KYUNGIN CHOI ,  Taehyeon KIM ,  HONGSHIK SHIN ,  TAEGON KIM ,  JAEYOUNG PARK ,  YUICHIRO SASAKI

IPC: H01L27/092 ,  H01L21/225 ,  H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

Abstract: A method of fabricating a semiconductor device includes pattering an upper portion of a substrate to form a first active pattern, the substrate including a semiconductor element having a first lattice constant, performing a selective epitaxial growth process on an upper portion of the first active pattern to form a first source/drain region, doping the first source/drain region with gallium, performing an annealing process on the first source/drain region doped with gallium, and forming a first contact pattern coupled to the first source/drain region. The first source/drain region includes a semiconductor element having a second lattice constant larger than the first lattice constant.

公开(公告)号：US20210020628A1

公开(公告)日：2021-01-21

申请号：US16817069

申请日：2020-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEUNGHA OH ,  PIL-KYU KANG ,  KUGHWAN KIM ,  WEONHONG KIM ,  YUICHIRO SASAKI ,  SANG WOO LEE ,  SUNGKEUN LIM ,  YONGHO HA ,  SANGJIN HYUN

IPC: H01L27/06 ,  H01L27/11578 ,  H01L27/11558 ,  H01L27/24 ,  H01L23/48

Abstract: A three-dimensional semiconductor device includes a lower substrate, a plurality of lower transistors disposed on the lower substrate, an upper substrate disposed on the lower transistors, a plurality of lower conductive lines disposed between the lower transistors and the upper substrate, and a plurality of upper transistors disposed on the upper substrate. At least one of the lower transistors is connected to a corresponding one of the lower conductive lines. Each of the upper transistors includes an upper gate electrode disposed on the upper substrate, a first upper source/drain pattern disposed in the upper substrate at a first side of the upper gate electrode, and a second upper source/drain pattern disposed in the upper substrate at a second, opposing side of the upper gate electrode. The upper gate electrode includes silicon germanium (SiGe).