公开(公告)号：US20190148521A1

公开(公告)日：2019-05-16

申请号：US16170842

申请日：2018-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gun Ho JO ,  Dae Joung KIM ,  Jae Mun KIM ,  Moon Han PARK ,  Tae Ho CHA ,  Jae Jong HAN

IPC: H01L29/66 ,  H01L21/02

Abstract: A method for fabricating a semiconductor device includes forming a fin type pattern protruding from a substrate and extending in a first direction, forming a field insulating layer covering a limited portion of the fin type pattern on the substrate such that the field insulating layer exposes a separate limited portion of the fin type pattern, forming a gate structure on the field insulating layer and the fin type pattern, the gate structure extending in a second direction, the second direction different from the first direction, forming a first barrier layer containing a nitrogen element in a first region of the field insulating layer, wherein the first region is exposed by the gate structure, adjacent to the gate structure and extending in the second direction and forming a gate spacer on the first barrier layer and on a side wall of the gate structure.

公开(公告)号：US20240363685A1

公开(公告)日：2024-10-31

申请号：US18507839

申请日：2023-11-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun Jun LIM ,  Tae Ho CHA ,  Su Bin LEE ,  Jeong Hyeon LEE ,  Hak Jong LEE ,  Seung Hyeon HONG

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes: an active pattern including a lower pattern and sheet patterns spaced apart from the lower pattern in a first direction; gate structures being separate in a second direction on the lower pattern. The gate structure includes a gate electrode and a gate insulating layer; a source/drain recess between the gate structures adjacent to each other; and a source/drain pattern filling the source/drain recess. The source/drain pattern includes: a first epitaxial region extended along a sidewall and a bottom surface of the source/drain recess, a second epitaxial region on the first epitaxial insertion epitaxial regions that are in contact with the first epitaxial region. The respective insertion epitaxial regions are spaced apart from each other and include silicon germanium. The first epitaxial region is disposed between the second epitaxial region and the insertion epitaxial region.

公开(公告)号：US20200243398A1

公开(公告)日：2020-07-30

申请号：US16848228

申请日：2020-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gun Ho JO ,  Dae Joung KIM ,  Jae Mun KIM ,  Moon Han PARK ,  Tae Ho CHA ,  Jae Jong HAN

IPC: H01L21/8238 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L21/84 ,  H01L21/8234 ,  H01L29/786

Abstract: A method for fabricating a semiconductor device includes forming a fin type pattern protruding from a substrate and extending in a first direction, forming a field insulating layer covering a limited portion of the fin type pattern on the substrate such that the field insulating layer exposes a separate limited portion of the fin type pattern, forming a gate structure on the field insulating layer and the fin type pattern, the gate structure extending in a second direction, the second direction different from the first direction, forming a first barrier layer containing a nitrogen element in a first region of the field insulating layer, wherein the first region is exposed by the gate structure, adjacent to the gate structure and extending in the second direction and forming a gate spacer on the first barrier layer and on a side wall of the gate structure.