公开(公告)号：US08956970B1

公开(公告)日：2015-02-17

申请号：US14200798

申请日：2014-03-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyoung-Won Oh ,  Tae-Jin Lim ,  Tae-Ki Hong

IPC: H01L21/4763 ,  H01L21/768

CPC classification number: H01L21/76879 ,  H01L21/28525 ,  H01L21/76816 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor pattern is formed on a substrate. An interlayer insulating layer is formed on the semiconductor pattern. A contact hole in the interlayer insulating layer is formed the semiconductor pattern is exposed. A lower plug is formed in the contact hole by a selective epitaxial growth (SEG) process. An upper plug is farmed in the contact hole on the lower plug by alternately and repeatedly performing a deposition process and an etching process.

Abstract translation: 在基板上形成半导体图形。 在半导体图案上形成层间绝缘层。 形成层间绝缘层中的接触孔，露出半导体图形。 通过选择性外延生长（SEG）工艺在接触孔中形成下部塞子。 通过交替地和重复地进行沉积处理和蚀刻工艺，在上塞子的接触孔中养殖上部塞子。

公开(公告)号：US20150050805A1

公开(公告)日：2015-02-19

申请号：US14200798

申请日：2014-03-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYOUNG-WON OH ,  Tae-Jin Lim ,  Tae-Ki Hong

IPC: H01L21/768

CPC classification number: H01L21/76879 ,  H01L21/28525 ,  H01L21/76816 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor pattern is formed on a substrate. An interlayer insulating layer is formed on the semiconductor pattern. A contact hole in the interlayer insulating layer is formed the semiconductor pattern is exposed. A lower plug is formed in the contact hole by a selective epitaxial growth (SEG) process. An upper plug is formed in the contact hole on the lower plug by alternately and repeatedly performing a deposition process and an etching process.

Abstract translation: 在基板上形成半导体图形。 在半导体图案上形成层间绝缘层。 形成层间绝缘层中的接触孔，露出半导体图形。 通过选择性外延生长（SEG）工艺在接触孔中形成下部塞子。 通过交替地和反复进行沉积处理和蚀刻工艺，在下塞子的接触孔中形成上塞子。