Abstract:
A semiconductor pattern is formed on a substrate. An interlayer insulating layer is formed on the semiconductor pattern. A contact hole in the interlayer insulating layer is formed the semiconductor pattern is exposed. A lower plug is formed in the contact hole by a selective epitaxial growth (SEG) process. An upper plug is farmed in the contact hole on the lower plug by alternately and repeatedly performing a deposition process and an etching process.
Abstract:
In a method of forming an epitaxial layer, a first plasma may be generated from a first reaction gas in a first region. The first plasma may be applied to a second reaction gas provided to a second region isolated from the first region to generate a second plasma from the second reaction gas. A blocking gas may be injected into the second region toward an edge of the substrate to help prevent the first plasma and the second plasma from being horizontally diffused. The first plasma and the second plasma may be applied to the substrate to form the epitaxial layer. Thus, the epitaxial layer may be formed at a temperature relatively lower than a temperature in a heating process.