公开(公告)号：US11869836B2

公开(公告)日：2024-01-09

申请号：US18105955

申请日：2023-02-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donghee Seo ,  Heonbok Lee ,  Tae-Yeol Kim ,  Daeyong Kim ,  Dohyun Lee

IPC: H01L23/49 ,  H01L29/78 ,  H01L23/498

CPC classification number: H01L23/49844 ,  H01L23/49811 ,  H01L29/78

Abstract: A semiconductor device including an interlayer insulating layer on a substrate; a conductive line on the interlayer insulating layer; and a contact plug penetrating the interlayer insulating layer, the contact plug being connected to the conductive line, wherein the contact plug includes an upper pattern penetrating an upper region of the interlayer insulating layer, the upper pattern protruding upwardly from a top surface of the interlayer insulating layer, the upper pattern includes a first portion penetrating the upper region of the interlayer insulating layer; and a second portion protruding upwardly from the top surface of the interlayer insulating layer, and a width of a lower region of the second portion in a direction parallel to a top surface of the substrate is greater than a width of an upper region of the second portion in the direction parallel to the top surface of the substrate.

公开(公告)号：US12009398B2

公开(公告)日：2024-06-11

申请号：US17932851

申请日：2022-09-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Seung Song ,  Tae-Yeol Kim ,  Jae-Jik Baek

IPC: H01L29/417 ,  H01L23/522 ,  H01L29/40

CPC classification number: H01L29/41775 ,  H01L23/5226 ,  H01L29/401

Abstract: A semiconductor device is disclosed. The semiconductor device includes a gate electrode on a substrate and extending in a first direction, source/drain patterns spaced apart from each other, in a second direction, with the gate electrode interposed therebetween, a gate contact electrically connected to the gate electrode, and an active contact electrically connected to at least one of the source/drain patterns. The active contact includes a lower contact pattern electrically connected to the at least one of the source/drain patterns, the lower contact pattern having a first width in the first direction, and an upper contact pattern electrically connected to a top surface of the lower contact pattern, the upper contact pattern having a second width in the first direction that is smaller than the first width. The upper contact pattern and the gate contact horizontally overlap each other.

公开(公告)号：US20210217861A1

公开(公告)日：2021-07-15

申请号：US17034088

申请日：2020-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYUN-SEUNG SONG ,  Tae-Yeol Kim ,  Jae-Jik Baek

IPC: H01L29/417 ,  H01L29/40 ,  H01L23/522

Abstract: A semiconductor device is disclosed. The semiconductor device includes a gate electrode on a substrate and extending in a first direction, source/drain patterns spaced apart from each other, in a second direction, with the gate electrode interposed therebetween, a gate contact electrically connected to the gate electrode, and an active contact electrically connected to at least one of the source/drain patterns. The active contact includes a lower contact pattern electrically connected to the at least one of the source/drain patterns, the lower contact pattern having a first width in the first direction, and an upper contact pattern electrically connected to a top surface of the lower contact pattern, the upper contact pattern having a second width in the first direction that is smaller than the first width. The upper contact pattern and the gate contact horizontally overlap each other.

公开(公告)号：US20240297232A1

公开(公告)日：2024-09-05

申请号：US18655409

申请日：2024-05-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Seung Song ,  Tae-Yeol Kim ,  Jae-Jik Baek

IPC: H01L29/417 ,  H01L23/522 ,  H01L29/40

CPC classification number: H01L29/41775 ,  H01L23/5226 ,  H01L29/401

Abstract: A semiconductor device is disclosed. The semiconductor device includes a gate electrode on a substrate and extending in a first direction, source/drain patterns spaced apart from each other, in a second direction, with the gate electrode interposed therebetween, a gate contact electrically connected to the gate electrode, and an active contact electrically connected to at least one of the source/drain patterns. The active contact includes a lower contact pattern electrically connected to the at least one of the source/drain patterns, the lower contact pattern having a first width in the first direction, and an upper contact pattern electrically connected to a top surface of the lower contact pattern, the upper contact pattern having a second width in the first direction that is smaller than the first width. The upper contact pattern and the gate contact horizontally overlap each other.

公开(公告)号：US11581253B2

公开(公告)日：2023-02-14

申请号：US17503723

申请日：2021-10-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donghee Seo ,  Heonbok Lee ,  Tae-Yeol Kim ,  Daeyong Kim ,  Dohyun Lee

IPC: H01L23/498 ,  H01L29/78

Abstract: A semiconductor device including an interlayer insulating layer on a substrate; a conductive line on the interlayer insulating layer; and a contact plug penetrating the interlayer insulating layer, the contact plug being connected to the conductive line, wherein the contact plug includes an upper pattern penetrating an upper region of the interlayer insulating layer, the upper pattern protruding upwardly from a top surface of the interlayer insulating layer, the upper pattern includes a first portion penetrating the upper region of the interlayer insulating layer; and a second portion protruding upwardly from the top surface of the interlayer insulating layer, and a width of a lower region of the second portion in a direction parallel to a top surface of the substrate is greater than a width of an upper region of the second portion in the direction parallel to the top surface of the substrate.

公开(公告)号：US11923426B2

公开(公告)日：2024-03-05

申请号：US17367988

申请日：2021-07-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Won Kang ,  Tae-Yeol Kim ,  Jeong Ik Kim ,  Rak Hwan Kim ,  Jun Ki Park ,  Chung Hwan Shin

IPC: H01L29/417 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/41775 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53266 ,  H01L29/0665 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/7851

Abstract: A semiconductor device capable of improving a device performance and a reliability is provided. The semiconductor device comprising a gate structure including a gate electrode on a substrate, a source/drain pattern on a side face of the gate electrode, on the substrate and, a source/drain contact connected to the source/drain pattern, on the source/drain pattern, a gate contact connected to the gate electrode, on the gate electrode, and a wiring structure connected to the source/drain contact and the gate contact, on the source/drain contact and the gate contact, wherein the wiring structure includes a first via plug, a second via plug, and a wiring line connected to the first via plug and the second via plug, the first via plug has a single conductive film structure, and the second via plug includes a lower via filling film, and an upper via filling film on the lower via filling film.

公开(公告)号：US20230011401A1

公开(公告)日：2023-01-12

申请号：US17932851

申请日：2022-09-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Seung Song ,  Tae-Yeol Kim ,  Jae-Jik Baek

IPC: H01L29/417 ,  H01L23/522 ,  H01L29/40

Abstract: A semiconductor device is disclosed. The semiconductor device includes a gate electrode on a substrate and extending in a first direction, source/drain patterns spaced apart from each other, in a second direction, with the gate electrode interposed therebetween, a gate contact electrically connected to the gate electrode, and an active contact electrically connected to at least one of the source/drain patterns. The active contact includes a lower contact pattern electrically connected to the at least one of the source/drain patterns, the lower contact pattern having a first width in the first direction, and an upper contact pattern electrically connected to a top surface of the lower contact pattern, the upper contact pattern having a second width in the first direction that is smaller than the first width. The upper contact pattern and the gate contact horizontally overlap each other.

公开(公告)号：US11482602B2

公开(公告)日：2022-10-25

申请号：US17034088

申请日：2020-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Seung Song ,  Tae-Yeol Kim ,  Jae-Jik Baek

IPC: H01L29/417 ,  H01L23/522 ,  H01L29/40

Abstract: A semiconductor device is disclosed. The semiconductor device includes a gate electrode on a substrate and extending in a first direction, source/drain patterns spaced apart from each other, in a second direction, with the gate electrode interposed therebetween, a gate contact electrically connected to the gate electrode, and an active contact electrically connected to at least one of the source/drain patterns. The active contact includes a lower contact pattern electrically connected to the at least one of the source/drain patterns, the lower contact pattern having a first width in the first direction, and an upper contact pattern electrically connected to a top surface of the lower contact pattern, the upper contact pattern having a second width in the first direction that is smaller than the first width. The upper contact pattern and the gate contact horizontally overlap each other.

公开(公告)号：US11152297B2

公开(公告)日：2021-10-19

申请号：US16893540

申请日：2020-06-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donghee Seo ,  Heonbok Lee ,  Tae-Yeol Kim ,  Daeyong Kim ,  Dohyun Lee

IPC: H01L29/78 ,  H01L23/498

Abstract: A semiconductor device including an interlayer insulating layer on a substrate; a conductive line on the interlayer insulating layer; and a contact plug penetrating the interlayer insulating layer, the contact plug being connected to the conductive line, wherein the contact plug includes an upper pattern penetrating an upper region of the interlayer insulating layer, the upper pattern protruding upwardly from a top surface of the interlayer insulating layer, the upper pattern includes a first portion penetrating the upper region of the interlayer insulating layer; and a second portion protruding upwardly from the top surface of the interlayer insulating layer, and a width of a lower region of the second portion in a direction parallel to a top surface of the substrate is greater than a width of an upper region of the second portion in the direction parallel to the top surface of the substrate.