公开(公告)号：US09065455B2

公开(公告)日：2015-06-23

申请号：US13777232

申请日：2013-02-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-sik Na ,  Seok-hun Hyun

IPC: G11C8/00 ,  H03L7/18 ,  G11C8/18 ,  G11C7/22 ,  H03L7/081

CPC classification number: H03L7/18 ,  G11C7/222 ,  G11C8/18 ,  H03L7/0812

Abstract: A delay locked loop (DLL) circuit having improved noise characteristics. The DLL circuit includes a first divider for generating a first divided signal by dividing an external clock; a second divider for generating a second divided signal by dividing an internal clock; a phase detector for detecting a phase difference between the first divided signal and the second divided signal; and an adjusting unit for synchronizing the internal clock and the external clock, based on the phase difference.

Abstract translation: 具有改善的噪声特性的延迟锁定环（DLL）电路。 所述DLL电路包括：第一分频器，用于通过划分外部时钟来产生第一分频信号; 第二分频器，用于通过分割内部时钟来产生第二分频信号; 相位检测器，用于检测第一分频信号和第二分频信号之间的相位差; 以及调整单元，用于基于相位差来同步内部时钟和外部时钟。