公开(公告)号：US09830960B2

公开(公告)日：2017-11-28

申请号：US15294890

申请日：2016-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang-kyo Lee ,  Won-young Lee ,  Bo-bae Shin ,  Jung-hwan Choi ,  Yong-cheol Bae ,  Seok-hun Hyun ,  Min-su Ahn

IPC: G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093

CPC classification number: G11C7/1057 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093

Abstract: A memory device may include a data output circuit configured to multiplex a plurality of data signals read from a memory cell array, wherein the data output circuit includes a clock boosting circuit configured to receive a plurality of internal clock signals generated based on a first power voltage, and to generate a plurality of boosted clock signals by boosting the plurality of internal clock signals based on a second power voltage having a voltage level greater than that of the first power voltage, and a data output driver configured to multiplex and output the plurality of data signals synchronized with the boosted clock signals.

公开(公告)号：US09065455B2

公开(公告)日：2015-06-23

申请号：US13777232

申请日：2013-02-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-sik Na ,  Seok-hun Hyun

IPC: G11C8/00 ,  H03L7/18 ,  G11C8/18 ,  G11C7/22 ,  H03L7/081

CPC classification number: H03L7/18 ,  G11C7/222 ,  G11C8/18 ,  H03L7/0812

Abstract: A delay locked loop (DLL) circuit having improved noise characteristics. The DLL circuit includes a first divider for generating a first divided signal by dividing an external clock; a second divider for generating a second divided signal by dividing an internal clock; a phase detector for detecting a phase difference between the first divided signal and the second divided signal; and an adjusting unit for synchronizing the internal clock and the external clock, based on the phase difference.

Abstract translation: 具有改善的噪声特性的延迟锁定环（DLL）电路。 所述DLL电路包括：第一分频器，用于通过划分外部时钟来产生第一分频信号; 第二分频器，用于通过分割内部时钟来产生第二分频信号; 相位检测器，用于检测第一分频信号和第二分频信号之间的相位差; 以及调整单元，用于基于相位差来同步内部时钟和外部时钟。