公开(公告)号：US11569349B2

公开(公告)日：2023-01-31

申请号：US17333080

申请日：2021-05-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho-Jun Kim ,  Woong Sik Nam ,  Mirco Cantoro

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/423 ,  H01L21/8234

Abstract: A semiconductor device includes first and second active patterns, a field insulating film between the first and second active patterns, a first gate structure intersecting the first active pattern and including a first gate electrode and a first gate spacer, a second gate structure intersecting the second active pattern and including a second gate electrode and a second gate spacer, a gate separation structure on the field insulating film between the first and second gate structures, the gate separation structure including a gate separation filling film on a gate separation liner, and a connecting spacer between the gate separation structure and the field insulating film, the connecting spacer protruding from a top surface of the field insulating film, and the gate separation liner contacting the connecting spacer and extending along a top surface and sidewalls of the connecting spacer and along the top surface of the field insulating film.

公开(公告)号：US20210257369A1

公开(公告)日：2021-08-19

申请号：US17313570

申请日：2021-05-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Beomyong Hwang ,  Min Hee Cho ,  Hei Seung Kim ,  Mirco Cantoro ,  Hyunmog Park ,  Woo Bin Song ,  Sang Woo Lee

IPC: H01L27/108 ,  G11C11/402

Abstract: A semiconductor device includes a substrate, a peripheral circuit layer, a first active pattern, a gate electrode, a first insulating layer, a conductive contact, and a second active pattern. The peripheral circuit layer is disposed on the substrate, and the peripheral circuit layer includes logic transistors and an interconnection layer that is disposed on the logic transistors. The first active pattern is disposed on the peripheral circuit layer. The gate electrode is disposed on a channel region of the first active pattern. The first insulating layer is disposed on the first active pattern and the gate electrode. The conductive contact is disposed in the first insulating layer and is electrically connected to a first source/drain region of the first active pattern, and the second active pattern is disposed on the first insulating layer. The channel region of the second active pattern vertically overlaps with the conductive contact.

公开(公告)号：US10734521B2

公开(公告)日：2020-08-04

申请号：US16211624

申请日：2018-12-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mirco Cantoro ,  Yeoncheol Heo

IPC: H01L29/78 ,  H01L29/06 ,  H01L27/088 ,  H01L29/417 ,  H01L29/10 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/8258

Abstract: The present disclosure relates to a field-effect transistor and a method of fabricating the same. A field-effect transistor includes a semiconductor substrate including a first semiconductor material having a first lattice constant, and a fin structure on the semiconductor substrate. The fin structure includes a second semiconductor material having a second lattice constant that is different from the first lattice constant. The fin structure further includes a lower portion that is elongated in a first direction, a plurality of upper portions protruding from the lower portion and elongated in a second direction that is different from the first direction, and a gate structure crossing the plurality of upper portions.

公开(公告)号：US10461187B2

公开(公告)日：2019-10-29

申请号：US16003959

申请日：2018-06-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mirco Cantoro ,  Yeon-cheol Heo ,  Maria Toledano Luque

IPC: H01L29/78 ,  H01L29/207 ,  H01L21/306 ,  H01L29/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/20 ,  H01L29/423

Abstract: An integrated circuit device may include a substrate including a main surface, a compound semiconductor nanowire extending from the main surface in a first direction perpendicular to the main surface and including a first section and a second section alternately arranged in the first direction, a gate electrode covering the first section, and a gate dielectric layer between the first section and the gate electrode. The first section and the second section may have the same composition as each other and may have different crystal phases from each other.

公开(公告)号：US09978881B2

公开(公告)日：2018-05-22

申请号：US15598675

申请日：2017-05-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mirco Cantoro ,  Yeon-cheol Heo ,  Maria Toledano Luque

IPC: H01L29/78 ,  H01L29/786 ,  H01L27/092 ,  H01L29/423 ,  H01L21/8238

CPC classification number: H01L29/78696 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/42392 ,  H01L29/78609 ,  H01L29/78618 ,  H01L29/78642

Abstract: An integrated circuit device includes a substrate, first and second fin active regions formed on the substrate and extending in a first direction parallel to a top surface of the substrate, a first gate structure disposed on a side surface of the first fin active region, a pair of first impurity regions respectively formed on a top portion and a bottom portion of the first fin active region, a second gate structure disposed on a side surface of the second fin active region, and a pair of second impurity regions respectively formed on a top portion or a bottom portion of the second fin active region, wherein the pair of first impurity regions vertically overlap each other, and the pair of second impurity regions do not vertically overlap each other.

公开(公告)号：US11955516B2

公开(公告)日：2024-04-09

申请号：US18102204

申请日：2023-01-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho-Jun Kim ,  Woong Sik Nam ,  Mirco Cantoro

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/0673 ,  H01L21/823481 ,  H01L29/4236 ,  H01L29/6656

Abstract: A semiconductor device includes first and second active patterns, a field insulating film between the first and second active patterns, a first gate structure intersecting the first active pattern and including a first gate electrode and a first gate spacer, a second gate structure intersecting the second active pattern and including a second gate electrode and a second gate spacer, a gate separation structure on the field insulating film between the first and second gate structures, the gate separation structure including a gate separation filling film on a gate separation liner, and a connecting spacer between the gate separation structure and the field insulating film, the connecting spacer protruding from a top surface of the field insulating film, and the gate separation liner contacting the connecting spacer and extending along a top surface and sidewalls of the connecting spacer and along the top surface of the field insulating film.

公开(公告)号：US11018137B2

公开(公告)日：2021-05-25

申请号：US16442769

申请日：2019-06-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Beomyong Hwang ,  Min Hee Cho ,  Hei Seung Kim ,  Mirco Cantoro ,  Hyunmog Park ,  Woo Bin Song ,  Sang Woo Lee

IPC: H01L27/10 ,  G11C11/40 ,  H01L27/108 ,  G11C11/402

Abstract: A semiconductor memory device includes a substrate, a first active pattern on the substrate, a gate electrode intersecting a channel region of the first active pattern, a first insulating layer covering the first active pattern and the gate electrode, a contact penetrating the first insulating layer so as to be electrically connected to a first source/drain region of the first active pattern, and a second active pattern on the first insulating layer. A channel region of the second active pattern vertically overlaps with the contact.

公开(公告)号：US10916655B2

公开(公告)日：2021-02-09

申请号：US16591958

申请日：2019-10-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woobin Song ,  Heiseung Kim ,  Mirco Cantoro ,  Sangwoo Lee ,  Minhee Cho ,  Beomyong Hwang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L29/161 ,  H01L21/02 ,  H01L21/28

Abstract: A ferroelectric semiconductor device includes an active region extending in one direction, a gate insulating layer crossing the active region, a ferroelectric layer disposed on the gate insulating layer and including a hafnium oxide, a gate electrode layer disposed on the ferroelectric layer, and source/drain regions disposed on the active region to be adjacent to both sides of the gate insulating layer, wherein the ferroelectric layer includes 20% or more of orthorhombic crystals, and an upper surface of the source/drain region is located at a level equal to or higher than an upper surface of the ferroelectric layer.

公开(公告)号：US10559673B2

公开(公告)日：2020-02-11

申请号：US16284843

申请日：2019-02-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungil Park ,  Changhee Kim ,  Yunil Lee ,  Mirco Cantoro ,  Junggun You ,  Donghun Lee

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L21/28 ,  H01L29/40 ,  H01L29/423 ,  H01L29/786 ,  H01L29/417

Abstract: A semiconductor device includes an active pillar on a substrate. A first source/drain region is disposed at a top end of the active pillar and has a greater width than the active pillar. A first insulating layer is disposed on a sidewall of the active pillar and a second insulating layer is disposed on at least a bottom surface of the first source/drain region. A gate electrode is disposed on the first insulating layer and the second insulating layer. A second source/drain region is disposed in the substrate at a bottom end of the active pillar. Methods of fabrication are also described.

公开(公告)号：US10361319B2

公开(公告)日：2019-07-23

申请号：US15981578

申请日：2018-05-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mirco Cantoro ,  Yeon-cheol Heo ,  Maria Toledano Luque

IPC: H01L29/786 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423

Abstract: An integrated circuit device includes a substrate, first and second fin active regions formed on the substrate and extending in a first direction parallel to a top surface of the substrate, a first gate structure disposed on a side surface of the first fin active region, a pair of first impurity regions respectively formed on a top portion and a bottom portion of the first fin active region, a second gate structure disposed on a side surface of the second fin active region, and a pair of second impurity regions respectively formed on a top portion or a bottom portion of the second fin active region, wherein the pair of first impurity regions vertically overlap each other, and the pair of second impurity regions do not vertically overlap each other.