公开(公告)号：US20250040156A1

公开(公告)日：2025-01-30

申请号：US18756794

申请日：2024-06-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taehong MIN ,  Minchul HAN

IPC: H10B99/00

Abstract: A memory device includes: first conductive lines extending in a first horizontal direction on a substrate; second conductive lines extending on the first conductive lines in a second horizontal direction; third conductive lines extending on the second conductive lines in the first horizontal direction; first memory cells provided at portions where the first conductive lines cross the second conductive lines; second memory cells provided at portions where the second conductive lines cross the third conductive lines; first dummy patterns horizontally spaced apart from the first memory cells and the second memory cells; and second dummy patterns horizontally spaced apart from the first memory cells and the second memory cells, the second dummy patterns facing the first dummy patterns, respectively, in the second horizontal direction. The plurality of first dummy patterns and the plurality of second dummy patterns are on different vertical levels from each other.

公开(公告)号：US20250062297A1

公开(公告)日：2025-02-20

申请号：US18678191

申请日：2024-05-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwon CHAE ,  Taehong MIN ,  Daehan SONG ,  Inwook JUNG

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/538 ,  H10B80/00

Abstract: A semiconductor package may comprise an interposer substrate including a substrate and a lower protective layer, a through-via passing through the substrate and the lower protective layer, a lower pad on the lower protective layer and in contact with the through-via, an interlayer insulating layer on an upper surface of the substrate, and an interconnection structure in the interlayer insulating layer, a plurality of first semiconductor chips on an upper surface of the interposer substrate and electrically connected to the interconnection structure, a second semiconductor chip on the upper surface of the interposer substrate apart from the plurality of first semiconductor chips and electrically connected to the interconnection structure, an encapsulant covering at least a portion of the plurality of first semiconductor chips and the second semiconductor chip and connection conductors on the lower surface of the lower protective layer and electrically connected to the lower pad.

公开(公告)号：US20220190242A1

公开(公告)日：2022-06-16

申请号：US17395043

申请日：2021-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heejung KIM ,  Taehong MIN ,  Chorong PARK ,  Joohee SEO ,  Eunsuk HWANG

IPC: H01L45/00 ,  H01L27/24

Abstract: A method of fabricating a three-dimensional semiconductor memory device includes forming a cell stack layer covering key and cell regions of a substrate and including a variable resistance layer and a switching layer, forming key mask patterns on the cell stack layer of the key region and cell mask patterns on the cell stack layer of the cell region, and simultaneously forming a plurality of key patterns on the key region and a plurality of memory cells on the cell region by etching the cell stack layer using the key and cell mask patterns as an etching mask. Each memory cell includes a variable resistance pattern and a switching pattern formed by etching the variable resistance layer and the switching layer. Each key pattern includes a dummy variable resistance pattern and a dummy switching pattern formed by etching the variable resistance layer and the switching layer.