公开(公告)号：US20240071983A1

公开(公告)日：2024-02-29

申请号：US18227697

申请日：2023-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bongken YU ,  Cheolsoo HAN ,  Kwangjin BAE ,  Youngjin JANG ,  Inwook JUNG ,  Minchul CHO

IPC: H01L23/00 ,  B23K3/06

CPC classification number: H01L24/75 ,  B23K3/0623 ,  H01L2224/75804

Abstract: A solder ball attaching apparatus includes a working die, having an internal space maintained in a vacuum state, and a plurality of lifting members installed on the working die to be movable upwardly and downwardly. The working die may be provided with an upper plate on which the lifting members are installed. The upper plate may be provided with an insertion groove, into which an upper end portion of the lifting member is inserted when the lifting member is lowered, and a locking groove into which a lower end portion of the lifting member is inserted when the lifting member is raised. The lifting member may be lowered by a chip when the chip is seated on the lifting member and may be raised by elastic restoring force when the chip is removed.

公开(公告)号：US20250062297A1

公开(公告)日：2025-02-20

申请号：US18678191

申请日：2024-05-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwon CHAE ,  Taehong MIN ,  Daehan SONG ,  Inwook JUNG

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/538 ,  H10B80/00

Abstract: A semiconductor package may comprise an interposer substrate including a substrate and a lower protective layer, a through-via passing through the substrate and the lower protective layer, a lower pad on the lower protective layer and in contact with the through-via, an interlayer insulating layer on an upper surface of the substrate, and an interconnection structure in the interlayer insulating layer, a plurality of first semiconductor chips on an upper surface of the interposer substrate and electrically connected to the interconnection structure, a second semiconductor chip on the upper surface of the interposer substrate apart from the plurality of first semiconductor chips and electrically connected to the interconnection structure, an encapsulant covering at least a portion of the plurality of first semiconductor chips and the second semiconductor chip and connection conductors on the lower surface of the lower protective layer and electrically connected to the lower pad.