公开(公告)号：US20220179302A1

公开(公告)日：2022-06-09

申请号：US17392788

申请日：2021-08-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjay KANG ,  Chorong PARK ,  Doogyu LEE ,  Seungyoon LEE ,  Jeongjin LEE

IPC: G03F1/36 ,  G03F1/22

Abstract: Disclosed are an overlay correction method, a method of evaluating an overlay correction operation, and a method of fabricating a semiconductor device using the overlay correction method. The overlay correction method may include measuring an overlay between center lines of lower and upper patterns on a wafer, fitting each of components of the overlay with a polynomial function to obtain first fitting quantities, and summing the first fitting quantities to construct a correction model. The components of the overlay may include overlay components, which are respectively measured in two different directions parallel to a top surface of a reticle. The highest order of the polynomial function may be determined as an order, which minimizes a difference between the polynomial function and each of the components of the overlay or corresponds to an inflection point in a graph of the difference with respect to the highest order of the polynomial function.

公开(公告)号：US20220190242A1

公开(公告)日：2022-06-16

申请号：US17395043

申请日：2021-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heejung KIM ,  Taehong MIN ,  Chorong PARK ,  Joohee SEO ,  Eunsuk HWANG

IPC: H01L45/00 ,  H01L27/24

Abstract: A method of fabricating a three-dimensional semiconductor memory device includes forming a cell stack layer covering key and cell regions of a substrate and including a variable resistance layer and a switching layer, forming key mask patterns on the cell stack layer of the key region and cell mask patterns on the cell stack layer of the cell region, and simultaneously forming a plurality of key patterns on the key region and a plurality of memory cells on the cell region by etching the cell stack layer using the key and cell mask patterns as an etching mask. Each memory cell includes a variable resistance pattern and a switching pattern formed by etching the variable resistance layer and the switching layer. Each key pattern includes a dummy variable resistance pattern and a dummy switching pattern formed by etching the variable resistance layer and the switching layer.