公开(公告)号：US20230205963A1

公开(公告)日：2023-06-29

申请号：US17961710

申请日：2022-10-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Akio Misaka ,  Noyoung Chung ,  Taekyum Kim ,  Sanghwa Lee ,  Woonhyuk Choi

IPC: G06F30/392 ,  G06F30/398

CPC classification number: G06F30/392 ,  G06F30/398

Abstract: A layout method of a semiconductor chip, includes designing a layout using a restriction rule such that a layout pattern having a length smaller than a first length in a first direction has to have a length smaller than a second length in a second direction, the second direction intersecting the first direction, generating a plurality of unit regions by partitioning the layout in the first direction, generating a plurality of target regions by adding a reference region to a partitioned edge of each of the plurality of unit regions, retargeting the plurality of target regions in parallel, and generating a correction layout by merging the plurality of retargeted target regions.