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公开(公告)号：US11092885B2
公开(公告)日：2021-08-17
申请号：US16845459
申请日：2020-04-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Akio Misaka , Noyoung Chung , Woonhyuk Choi
IPC: G06F30/30 , G03F1/36 , G06F30/392 , G06F30/367 , G06F30/3953 , G06F30/398
Abstract: A method of manufacturing a semiconductor device includes randomly placing a plurality of standard cells from a library in which the standard cells are pre-stored, designing an interconnection pattern in which the standard cells are connected randomly to each other, connecting the standard cells according to the interconnection pattern to generate a virtual layout, performing an optical proximity correction operation on the virtual layout using an optical proximity correction (OPC) model, and forming and verifying a mask corresponding to the virtual layout on which the optical proximity correction operation is performed.
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公开(公告)号：US20250093763A1
公开(公告)日：2025-03-20
申请号：US18818984
申请日：2024-08-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Akio Misaka , Bongkeun Kim , Ran Lee , Sanghwa Lee , Wonjoo Im
Abstract: A photomask for a photolithography process includes a mask substrate, a reflective multilayer on the mask substrate, and a light absorber pattern on the reflective multilayer and having hole patterns, wherein the hole patterns include a main hole pattern for pattern transfer onto a wafer, first sub-resolution assist feature (SRAF) hole patterns arranged at regular intervals to provide honeycomb lattices in a first region centered around the main hole pattern and having a first pitch less than or equal to a diffraction limit in the photolithography process, and second SRAF hole patterns arranged at regular intervals to surround the main hole pattern and the first SRAF patterns and providing honeycomb lattices in a second region centered around the main hole pattern and surrounding the first region, the second SRAF hole patterns being arranged with a second pitch less than or equal to the diffraction limit in the photolithography process.
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Patent Agency Ranking
3.发明公开公开(公告)号：US20230205963A1
公开(公告)日：2023-06-29
申请号：US17961710
申请日：2022-10-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Akio Misaka , Noyoung Chung , Taekyum Kim , Sanghwa Lee , Woonhyuk Choi
IPC: G06F30/392 , G06F30/398
CPC classification number: G06F30/392 , G06F30/398
Abstract: A layout method of a semiconductor chip, includes designing a layout using a restriction rule such that a layout pattern having a length smaller than a first length in a first direction has to have a length smaller than a second length in a second direction, the second direction intersecting the first direction, generating a plurality of unit regions by partitioning the layout in the first direction, generating a plurality of target regions by adding a reference region to a partitioned edge of each of the plurality of unit regions, retargeting the plurality of target regions in parallel, and generating a correction layout by merging the plurality of retargeted target regions.
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公开(公告)号：US10962874B2
公开(公告)日：2021-03-30
申请号：US16382351
申请日：2019-04-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Akio Misaka , No-young Chung , Ki-soo Kim
Abstract: A method of manufacturing a semiconductor device includes performing extreme ultraviolet (EUV) lithography that uses a mask for the EUV lithography manufactured by using a design layout on which optical proximity correction (OPC) is performed, and performing the OPC includes dividing respective patterns included in the design layout into partial patterns, classifying the partial patterns into a plurality of partial pattern groups, performing a first OPC on the design layout, and performing a second OPC that is different from the first OPC on the design layout on which the first OPC is performed, wherein performing the first OPC is performed on representative patterns selected from the plurality of partial pattern groups.
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公开(公告)号：US20200064728A1
公开(公告)日：2020-02-27
申请号：US16382351
申请日：2019-04-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Akio Misaka , No-young Chung , Ki-soo KIM
Abstract: A method of manufacturing a semiconductor device includes performing extreme ultraviolet (EUV) lithography that uses a mask for the EUV lithography manufactured by using a design layout on which optical proximity correction (OPC) is performed, and performing the OPC includes dividing respective patterns included in the design layout into partial patterns, classifying the partial patterns into a plurality of partial pattern groups, performing a first OPC on the design layout, and performing a second OPC that is different from the first OPC on the design layout on which the first OPC is performed, wherein performing the first OPC is performed on representative patterns selected from the plurality of partial pattern groups.
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公开(公告)号：US11698581B2
公开(公告)日：2023-07-11
申请号：US17360365
申请日：2021-06-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Akio Misaka , Changsoo Kim , Noyoung Chung
IPC: G03F1/36 , G06F30/392 , G06N20/00
CPC classification number: G03F1/36 , G06F30/392 , G06N20/00
Abstract: A non-transitory computer-readable medium storing codes that, when executed by a processor, cause the processor to perform operations of receiving full chip data including specific patterns of a first layout, extracting a representative pattern of the first layout from the full chip data, generating a vector of the extracted representative pattern, generating a first data set based on the generated vector, generating a machine learning model by performing machine learning with respect to the first data set, executing an optical proximity correction (OPC) with respect to the specific patterns of the first layout by using the machine learning model, and generating a second layout based on a result of executing the OPC may be provided.
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公开(公告)号：US20210063867A1
公开(公告)日：2021-03-04
申请号：US16845459
申请日：2020-04-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Akio Misaka , NOYOUNG CHUNG , WOONHYUK CHOI
IPC: G03F1/36 , G06F30/392 , G06F30/398 , G06F30/3953 , G06F30/367
Abstract: A method of manufacturing a semiconductor device includes randomly placing a plurality of standard cells from a library in which the standard cells are pre-stored, designing an interconnection pattern in which the standard cells are connected randomly to each other, connecting the standard cells according to the interconnection pattern to generate a virtual layout, performing an optical proximity correction operation on the virtual layout using an optical proximity correction (OPC) model, and forming and verifying a mask corresponding to the virtual layout on which the optical proximity correction operation is performed.
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