公开(公告)号：US20240422963A1

公开(公告)日：2024-12-19

申请号：US18604584

申请日：2024-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYO-SUK CHAE ,  Tai Uk Rim ,  Jin-seong Lee ,  Hee Jae Choi ,  Jung-Hoon Han ,  Byung Ha Kang ,  Gyu Taek Shin ,  Shin Woo Jeong

IPC: H10B12/00

Abstract: A semiconductor memory device includes a substrate including a device isolation film defining active regions; and cell gate structures in trenches, including first areas and second areas, the cell gate structures extending to intersect the active regions, each of the cell gate structures includes a cell gate insulating layer, extending along inner sidewalls of the trenches, a first gate dielectric film, on sidewalls of the cell gate insulating layer, in a first area of the trench, a second gate dielectric film, on the sidewalls of the cell gate insulating layer, in a second area of the trench, and a cell gate electrode structure, including a first gate electrode layer on sidewalls of the first gate dielectric film and a second gate electrode layer on sidewalls of the second gate dielectric film in the second area.

公开(公告)号：US20240121945A1

公开(公告)日：2024-04-11

申请号：US18347927

申请日：2023-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Seong Lee ,  Tai Uk Rim ,  Ji Hun Kim ,  Kyo-Suk Chae

IPC: H10B12/00

CPC classification number: H10B12/34 ,  H10B12/053 ,  H10B12/315

Abstract: A semiconductor memory device comprises a substrate including a first source/drain region and a second source/drain region, a trench between the first source/drain region and the second source/drain region and formed in the substrate, a cell gate insulating layer on sidewalls and a bottom surface of the trench, a cell gate electrode on the cell gate insulating layer, a work function control pattern on the cell gate electrode, including N-type impurities and a cell gate capping pattern on the work function control pattern. The work function control pattern includes a semiconductor material. The work function control pattern includes a first region and a second region between the first region and the cell gate electrode. A concentration of the N-type impurities in the first region is greater than a concentration of the N-type impurities in the second region.