公开(公告)号：US12283502B2

公开(公告)日：2025-04-22

申请号：US17543025

申请日：2021-12-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young Wook Kim ,  Sang Min Kim ,  Ji Hun Kim ,  Gi-Nam Park ,  Chul-Jun Park ,  Yong-Jun Ahn ,  Youn Gon Oh ,  Byung Kook Yoo ,  Hyun Woo Lee ,  Jeong Hun Lim

IPC: G06F7/00 ,  H01L21/67 ,  H01L21/677

Abstract: A substrate transfer device includes a transfer unit configured to transfer, in a first direction, a carrier in which substrates are stored, an upper interface unit configured to move the transfer unit, a lower interface unit configured to receive the carrier from the transfer unit, and a controller configured to control the upper interface unit and the lower interface unit integrally such that the transfer unit and the carrier move in the first direction at the same time.

公开(公告)号：US20240121945A1

公开(公告)日：2024-04-11

申请号：US18347927

申请日：2023-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Seong Lee ,  Tai Uk Rim ,  Ji Hun Kim ,  Kyo-Suk Chae

IPC: H10B12/00

CPC classification number: H10B12/34 ,  H10B12/053 ,  H10B12/315

Abstract: A semiconductor memory device comprises a substrate including a first source/drain region and a second source/drain region, a trench between the first source/drain region and the second source/drain region and formed in the substrate, a cell gate insulating layer on sidewalls and a bottom surface of the trench, a cell gate electrode on the cell gate insulating layer, a work function control pattern on the cell gate electrode, including N-type impurities and a cell gate capping pattern on the work function control pattern. The work function control pattern includes a semiconductor material. The work function control pattern includes a first region and a second region between the first region and the cell gate electrode. A concentration of the N-type impurities in the first region is greater than a concentration of the N-type impurities in the second region.

公开(公告)号：US11984338B2

公开(公告)日：2024-05-14

申请号：US17745595

申请日：2022-05-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youn Gon Oh ,  Ji Hun Kim ,  Seung Gu Bang ,  Sung-Hoon Lee ,  Ho Chan Lee ,  Hyeong Seok Choo

IPC: H01L21/677 ,  B66C19/00

CPC classification number: H01L21/6773 ,  B66C19/00 ,  H01L21/67736

Abstract: A substrate transfer system capable of performing efficient distribution exchange between fabricating facilities is provided. The substrate transfer system includes a lower rail, an upper rail which is located above the lower rail from a ground plane, and extends to be parallel to the lower rail, a conveyor which extends to intersect the lower rail and the upper rail, below the lower rail, a first lower transport unit which transports a first carrier along the lower rail and unloads the first carrier onto the conveyor, and a first upper transport unit which transports a second carrier along the upper rail and unloads the second carrier onto the conveyor, wherein the conveyor includes a linear module which moves the first carrier and the second carrier in a linear direction, and a turning module which turns the first carrier and the second carrier.

公开(公告)号：US11175717B2

公开(公告)日：2021-11-16

申请号：US16086084

申请日：2017-03-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Jin Kim ,  Ji Hun Kim ,  Gwang Hui Lee ,  Sung Jun Lee ,  Woo Jun Jung ,  Min Jung Kim

IPC: G09G5/36 ,  G06F1/3225 ,  G06F3/14 ,  G09G5/393 ,  G09G5/397

Abstract: Various examples of the present invention relate to an electronic device comprising: a graphic buffer for storing graphic information received from an application; a frame buffer for storing the graphic information to be displayed on a display; and a processor, wherein the processor is configured to: store, in the graphic buffer, first graphic information received from a first layer; store, in the frame buffer, second graphic information received from a second layer; store, in the frame buffer, the first graphic information stored in the graphic buffer; and simultaneously display the first graphic information and the second graphic information, stored in the frame buffer, through the display functionally connected with the processor. In addition, other examples identifiable through the specification are possible.

公开(公告)号：US10249627B2

公开(公告)日：2019-04-02

申请号：US15621315

申请日：2017-06-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Hoon Han ,  Dong Wan Kim ,  Ji Hun Kim ,  Jae Joon Song ,  Hiroshi Takeda

IPC: H01L27/108 ,  H01L49/02

Abstract: A semiconductor device is provided. The semiconductor device includes an upper interlayer insulating layer disposed on a substrate. A first electrode spaced apart from the upper interlayer insulating layer is disposed on the substrate. A contact structure penetrating the upper interlayer insulating layer is disposed on the substrate. An upper support layer having a first portion covering an upper surface of the upper interlayer insulating layer, to surround an upper side surface of the contact structure, and a second portion extending in a horizontal direction from the first portion and surrounding an upper side surface of the first electrode, is disposed. A dielectric conformally covering the first electrode and a second electrode on the dielectric are disposed.

公开(公告)号：US09484409B2

公开(公告)日：2016-11-01

申请号：US14846176

申请日：2015-09-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun-Sun Lee ,  Junhwa Song ,  Ji Hun Kim ,  Jeonghoon Oh

IPC: H01L29/76 ,  H01L29/94 ,  H01L29/10 ,  H01L29/08 ,  H01L29/04 ,  H01L27/11 ,  G11C7/06 ,  G11C11/4091 ,  G11C11/412

CPC classification number: H01L29/1033 ,  G11C7/065 ,  G11C11/4091 ,  G11C11/412 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/1079

Abstract: A semiconductor device includes a semiconductor substrate including a well dopant layer having a first conductivity type, a gate electrode on the well dopant layer, a channel dopant layer in the well dopant layer and spaced apart from a top surface of the semiconductor substrate, a channel region between the gate electrode and the channel dopant layer, and source/drain regions in the well dopant layer at both sides of the gate electrode. The channel dopant layer and the channel region have the first conductivity type. The source/drain regions have a second conductivity type. A concentration of dopants having the first conductivity type in the channel dopant layer is higher than a concentration of dopants having the first conductivity type in the channel region. The semiconductor device may be used in a sense amplifier of a memory device.

Abstract translation: 一种半导体器件包括：半导体衬底，包括具有第一导电类型的阱掺杂剂层，阱掺杂剂层上的栅极电极，阱掺杂剂层中的沟道掺杂剂层，并且与半导体衬底的顶表面间隔开;沟道 栅电极和沟道掺杂剂层之间的区域以及栅电极两侧的阱掺杂剂层中的源/漏区。 沟道掺杂剂层和沟道区具有第一导电类型。 源极/漏极区域具有第二导电类型。 在沟道掺杂剂层中具有第一导电类型的掺杂剂的浓度高于沟道区中具有第一导电类型的掺杂剂的浓度。 半导体器件可以用在存储器件的读出放大器中。

公开(公告)号：US11982705B2

公开(公告)日：2024-05-14

申请号：US17690317

申请日：2022-03-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youn Gon Oh ,  Ji Hun Kim ,  Sae Yun Ko ,  Gil Ho Gu ,  Dong Su Kim ,  Eun Hee Lee ,  Ho Chan Lee ,  Seong Sil Jeong ,  Seong Pyo Hong

IPC: G01R31/28 ,  H01L21/673 ,  H01L21/677

CPC classification number: G01R31/2831 ,  H01L21/6735 ,  H01L21/6773

Abstract: A substrate analysis apparatus is provided. The substrate analysis includes: an interlayer conveying module configured to transport a first FOUP; an exchange module which is connected to the interlayer conveying module, and configured to transfer a wafer from the first FOUP to a second FOUP; a pre-processing module configured to form a test wafer piece using the wafer inside the second FOUP; an analysis module configured to analyze the test wafer piece; and a transfer rail configured to transport the second FOUP containing the wafer and a tray containing the test wafer piece. The wafer includes a first identifier indicating information corresponding to the wafer, the test wafer piece includes a second identifier indicating information generated by the pre-processing module which corresponds to the test wafer piece, and the analysis module is configured to analyze the first identifier and the second identifier in connection with each other.

公开(公告)号：US20220336241A1

公开(公告)日：2022-10-20

申请号：US17543025

申请日：2021-12-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young Wook Kim ,  Sang Min Kim ,  Ji Hun Kim ,  Gi-Nam Park ,  Chul-Jun Park ,  Yong-Jun Ahn ,  Youn Gon Oh ,  Byung Kook Yoo ,  Hyun Woo Lee ,  Jeong Hun Lim

IPC: H01L21/67 ,  H01L21/677

Abstract: A substrate transfer device includes a transfer unit configured to transfer, in a first direction, a carrier in which substrates are stored, an upper interface unit configured to move the transfer unit, a lower interface unit configured to receive the carrier from the transfer unit, and a controller configured to control the upper interface unit and the lower interface unit integrally such that the transfer unit and the carrier move in the first direction at the same time.

公开(公告)号：US20240124230A1

公开(公告)日：2024-04-18

申请号：US18217058

申请日：2023-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youn Gon Oh ,  Ji Hun Kim ,  Sang Hyuk Park ,  Young-Kyu Kim

IPC: B65G1/06 ,  B65G1/04 ,  B65G49/06

CPC classification number: B65G1/065 ,  B65G1/0414 ,  B65G49/062 ,  B65G49/067 ,  B65G2201/0297

Abstract: An inter-floor transport system includes a first interface unit at a first floor and configured to receive containers from a transport vehicle, and a car configured to receive containers from the first interface unit at the first floor and move containers to a second floor, where the car includes a cage, a storage unit in the cage and including a plurality of storage areas, and an arrangement unit in the cage, the arrangement unit being configured to receive containers from the first interface unit and store containers in respective storage areas of the plurality of storage areas of the storage unit.

公开(公告)号：US20240006215A1

公开(公告)日：2024-01-04

申请号：US18195757

申请日：2023-05-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Hyuk PARK ,  Youn Gon Oh ,  Hyuk Kwon ,  Young-Kyu Kim ,  Ji Hun Kim ,  Sung-Hoon Lee ,  Jeong Kwan Jung

IPC: H01L21/677

CPC classification number: H01L21/67733 ,  H01L21/67769 ,  H01L21/6773 ,  H01L21/67706 ,  H01L21/67736

Abstract: A wafer storage and transport system includes a ceiling surface which includes a first surface and a second surface, a first traveling rail installed on the second surface, a second traveling rail which is spaced apart from the first surface in a third direction, and extends in a first direction, a transport unit which is movable in the first direction along the second traveling rail and transports a FOUP, storage spaces installed on the first surface and which may store the FOUP, an interface port installed on the second surface and which temporarily stores the FOUP, and an OHT which is movable along the first traveling rail, wherein the transport unit grasps the FOUP arranged in the storage spaces and transports the FOUP to the interface port, and the OHT grasps the FOUP temporarily stored in the interface port and transports the FOUP to a semiconductor facility.