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    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
    2.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20190027480A1

    公开(公告)日：2019-01-24

    申请号：US15920628

    申请日：2018-03-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyun-jung Lee ,  Dongsoo Woo ,  Jin-Seong Lee ,  Namho Jeon ,  Jaeho Hong

    IPC: H01L27/108

    Abstract: A semiconductor memory device includes a separation member defining active regions of a substrate. Gate lines intersect the active regions and are each buried in a trench formed in the substrate. Each of the gate lines includes a lower electrode structure and an upper electrode structure on the lower electrode structure. The upper electrode structure includes a source layer substantially covering a sidewall of the trench and including a work-function adjustment element. A conductive layer is on the source layer. A work-function adjustment layer is disposed between the source layer and the conductive layer. The work-function adjustment layer includes a material different from that of the source layer and is doped with the work-function adjustment element.

    Semiconductor memory device and method of manufacturing the same
    3.
    发明授权
    Semiconductor memory device and method of manufacturing the same 有权

    公开(公告)号：US10312243B2

    公开(公告)日：2019-06-04

    申请号：US15920628

    申请日：2018-03-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyun-jung Lee ,  Dongsoo Woo ,  Jin-Seong Lee ,  Namho Jeon ,  Jaeho Hong

    IPC: H01L29/43 ,  H01L29/49 ,  H01L27/108 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/51

    Abstract: A semiconductor memory device includes a separation member defining active regions of a substrate. Gate lines intersect the active regions and are each buried in a trench formed in the substrate. Each of the gate lines includes a lower electrode structure and an upper electrode structure on the lower electrode structure. The upper electrode structure includes a source layer substantially covering a sidewall of the trench and including a work-function adjustment element. A conductive layer is on the source layer. A work-function adjustment layer is disposed between the source layer and the conductive layer. The work-function adjustment layer includes a material different from that of the source layer and is doped with the work-function adjustment element.

    SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME
    4.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME 审中-公开

    公开(公告)号：US20240121945A1

    公开(公告)日：2024-04-11

    申请号：US18347927

    申请日：2023-07-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jin-Seong Lee ,  Tai Uk Rim ,  Ji Hun Kim ,  Kyo-Suk Chae

    IPC: H10B12/00

    CPC classification number: H10B12/34 ,  H10B12/053 ,  H10B12/315

    Abstract: A semiconductor memory device comprises a substrate including a first source/drain region and a second source/drain region, a trench between the first source/drain region and the second source/drain region and formed in the substrate, a cell gate insulating layer on sidewalls and a bottom surface of the trench, a cell gate electrode on the cell gate insulating layer, a work function control pattern on the cell gate electrode, including N-type impurities and a cell gate capping pattern on the work function control pattern. The work function control pattern includes a semiconductor material. The work function control pattern includes a first region and a second region between the first region and the cell gate electrode. A concentration of the N-type impurities in the first region is greater than a concentration of the N-type impurities in the second region.

    Capacitorless memory device
    7.
    发明授权
    Capacitorless memory device 有权
    无电容存储器件

    公开(公告)号：US08941173B2

    公开(公告)日：2015-01-27

    申请号：US13775586

    申请日：2013-02-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seung-Uk Han ,  Jae-Hoon Lee ,  Jun-Su Kim ,  Satoru Yamada ,  Jin-Seong Lee ,  Nam-Ho Jeon

    IPC: H01L29/66 ,  H01L27/088 ,  H01L27/11 ,  H01L27/108

    CPC classification number: H01L27/088 ,  H01L27/108 ,  H01L27/11

    Abstract: According to an example embodiment of inventive concepts, a capacitorless memory device includes a capacitorless memory cell that includes a bit line on a substrate; a read transistor, and a write transistor. The read transistor may include first to third impurity layers stacked in a vertical direction on the bit line. The first and third layers may be a first conductive type, and the second impurity layer may be a second conductive type that differs from the first conductive type. The write transistor may include a source layer, a body layer, and a drain layer stacked in the vertical direction on the substrate, and a gate line that is adjacent to a side surface of the body layer. The gate line may be spaced apart from the side surface of the body layer. The source layer may be adjacent to a side surface of the second impurity layer.

    Abstract translation: 根据本发明构思的示例性实施例，一种无电容器存储器件包括：无电容器存储器单元，其在衬底上包括位线; 读取晶体管和写入晶体管。 读取晶体管可以包括在位线上沿垂直方向堆叠的第一至第三杂质层。 第一和第三层可以是第一导电类型，并且第二杂质层可以是不同于第一导电类型的第二导电类型。 写入晶体管可以包括在基板上沿垂直方向堆叠的源极层，主体层和漏极层，以及与主体层的侧表面相邻的栅极线。 栅极线可以与主体层的侧表面间隔开。 源极层可以与第二杂质层的侧表面相邻。

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