-
公开(公告)号：US20240054179A1
公开(公告)日：2024-02-15
申请号：US17934171
申请日：2022-09-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Mehran ELYASI , Zongwang LI , Rekha PITCHUMANI , Tong ZHANG , Heekwon PARK
CPC classification number: G06F17/16 , G06F9/30036
Abstract: A system and method for inference using an embedding table. In some embodiments, the method includes forming a culled index vector including a first index, and requesting a weight vector corresponding to the first index. The first index may be a first element of a first index vector, the first index being culled within the culled index vector.
-
公开(公告)号：US20230409196A1
公开(公告)日：2023-12-21
申请号：US17885520
申请日：2022-08-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Tong ZHANG , Heekwon PARK , Rekha PITCHUMANI , Yang Seok KI
IPC: G06F3/06
CPC classification number: G06F3/0604 , G06F3/064 , G06F3/0689
Abstract: A system is disclosed. The system may include a processor that may issue a byte level protocol request including a byte address. The system may also include a first storage device and a second storage device. The first storage device and the second storage device may support a cache coherent interconnect protocol, the cache coherent interconnect protocol including a block level protocol and a byte level protocol. The first storage device and the second storage device are included in a redundant array of independent disks (RAID). The first storage device may include a first address range, and the second storage device may include a second address range. The second storage device may provide a RAID address range associated with the first address range and the second address range. A decoder associated with the second storage device may be configured to receive the request from the processor. The decoder may determine that the byte address in the RAID address range is associated with a target address range.
-
公开(公告)号：US20220374260A1
公开(公告)日：2022-11-24
申请号：US17686404
申请日：2022-03-03
Applicant: Samsung Electronics Co., Ltd.
Inventor： Tong ZHANG , Jing YANG , Rekha PITCHUMANI
Abstract: A method for computation may include performing a first computation using a first system, wherein the first computation may be based, at least in part, on a first computation basis, performing a second computation using a second system, wherein the second computation may be based, at least in part, on a second computation basis, and coordinating the first computation and the second computation. The first computation basis may include a clock basis, and the second computation basis may include an event basis. The first computation may include a first operation, the second computation may include a second operation, and the coordinating the first computation and the second computation may include coordinating the first computation and the second computation based on the first operation and the second operation. The first operation may include an application computation operation, and the second operation may include a device computation operation.
-
公开(公告)号：US20240361952A1
公开(公告)日：2024-10-31
申请号：US18427816
申请日：2024-01-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： Rekha PITCHUMANI , Yang Seok KI , Zongwang LI , Marie Mai NGUYEN , Tong ZHANG
IPC: G06F3/06
CPC classification number: G06F3/0656 , G06F3/0604 , G06F3/0679
Abstract: A device may include cache media, storage media, a communication interface configured to communicate with the cache media and the storage media, and at least one control circuit to configure a portion of the storage media as visible memory, and configure a portion of the cache media as a cache for the portion of the storage media. The portion of the storage media may be a first portion of the storage media, and the at least one control circuit may be to configure a second portion of the storage media to persist the portion of the cache media. The portion of the storage media may be a first portion of the storage media, and the at least one control circuit may be to configure a second portion of the storage media as visible storage.
-
公开(公告)号：US20240061786A1
公开(公告)日：2024-02-22
申请号：US17986889
申请日：2022-11-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Da ZHANG , Jing YANG , Tong ZHANG , Shuyi PEI , Rekha PITCHUMANI
IPC: G06F12/0891 , G06F12/0804
CPC classification number: G06F12/0891 , G06F12/0804 , G06F2212/1024
Abstract: An apparatus may include at least one memory, and at least one processor configured to determine an accessibility of a first version of a page, wherein the first version of the page may be stored in the at least one memory, and perform, based on the accessibility of the first version of the page, an access of at least a portion of a second version of the page, wherein the second version of the page is stored in the at least one memory. The accessibility of the first version of the page may be based on an erase operation of the first version of the page. The access of the at least a portion of the second version of the page may include an access of a cache line of the second version of the page.
-
Patent Agency Ranking
公开(公告)号：US20230409480A1
公开(公告)日：2023-12-21
申请号：US17885519
申请日：2022-08-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Tong ZHANG , Heekwon PARK , Rekha PITCHUMANI , Yang Seok KI
IPC: G06F12/0817 , G06F3/06
CPC classification number: G06F12/0828 , G06F3/0689 , G06F3/0655 , G06F3/0604 , G06F2212/621
Abstract: A system is disclosed. A first storage device may supporting a cache coherent interconnect protocol, the cache coherent interconnect protocol including a block level protocol and a byte level protocol. A second storage device may also support the cache coherent interconnect protocol. A redundant array of independent disks (RAID) circuit may communicate with the first storage device and the second storage device. The RAID circuit may apply a RAID level to the first storage device and the second storage device. The RAID circuit may be configured to receive a request using the byte level protocol and to access data on the first storage device.
-
公开(公告)号：US20230297517A1
公开(公告)日：2023-09-21
申请号：US18123252
申请日：2023-03-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Marie Mai NGUYEN , Heekwon PARK , Tong ZHANG , Ho Bin LEE , Yang Seok KI , Rekha PITCHUMANI
CPC classification number: G06F12/1491 , G06F12/0269 , G06F2212/1052
Abstract: A method includes storing, at a computing device, access granularity criteria associated with a memory area. The method further includes receiving a memory operation request requesting access to a first portion of the memory area at the first access granularity. The method further includes in response to the memory operation request satisfying the access granularity criteria, sending, from the computing device, a command to a storage device based on the memory operation request.
-
公开(公告)号：US20230050808A1
公开(公告)日：2023-02-16
申请号：US17494823
申请日：2021-10-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： Zongwang LI , Tong ZHANG , Rekha PITCHUMANI , Yang Seok KI
Abstract: A method for memory access may include receiving, at a device, a first memory access request for a parallel workload, receiving, at the device, a second memory access request for the parallel workload, processing, by a first logical device of the device, the first memory access request, and processing, by a second logical device of the device, the second memory access request. Processing the first memory access request and processing the second memory access request may include parallel processing the first and second memory access requests. The first logical device may include one or more first resources. The method may further include configuring the first logical device based on one or more first parameters of the parallel workload. The method may further include allocating one or more first resources to the first logical device based on at least one of the one or more first parameters of the parallel workload.
-
公开(公告)号：US20230017019A1
公开(公告)日：2023-01-19
申请号：US17507775
申请日：2021-10-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Heekwon PARK , Tong ZHANG , Yang Seok KI
IPC: G06F3/06
Abstract: A method may include receiving, from a process, a memory allocation request for a memory system comprising a first channel having a first channel utilization and a second channel having a second channel utilization, selecting, based on the first channel utilization and the second channel utilization, the first channel, and allocating, to the process, a page of memory from the first channel. The selecting may include selecting the first channel based on a balanced random policy. The selecting may include generating a ticket based on a random number and a number of free pages, comparing the ticket to a number of free pages of the first channel, and selecting the first channel based on the comparing. The selecting may include selecting the first channel based on a least used channel policy.
-
公开(公告)号：US20240403241A1
公开(公告)日：2024-12-05
申请号：US18630988
申请日：2024-04-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Zongwang LI , Tong ZHANG , Rekha PITCHUMANI
Abstract: A device may include a storage medium, a cache medium, a buffer medium, and at least one control circuit configured to perform one or more operations including receiving a first request to access the storage medium, accessing, based on the first request, the cache medium, copying, from a portion of the storage medium to the buffer medium, data, modifying, based on the copying, an availability of the at least a portion of the storage medium, receiving a second request to access the storage medium, and accessing, based on the second request, the buffer medium. The one or more operations may include determining a location of data associated with the second request, and accessing, based on the determining, the buffer medium. The one or more operations may include receiving information about a location of data associated with the second request, and accessing, based on the information, the buffer medium.
-
-
-
-
-
-
-
-
-
Search Results
12
records
(took 0.025 seconds)
